1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 */
6
7 #include <common.h>
8 #include <hwconfig.h>
9 #include <i2c.h>
10 #include <spi.h>
11 #include <linux/libfdt.h>
12 #include <fdt_support.h>
13 #include <pci.h>
14 #include <mpc83xx.h>
15 #include <vsc7385.h>
16 #include <netdev.h>
17 #include <fsl_esdhc.h>
18 #include <asm/io.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_mpc83xx_serdes.h>
21
22 /*
23 * The following are used to control the SPI chip selects for the SPI command.
24 */
25 #ifdef CONFIG_MPC8XXX_SPI
26
27 #define SPI_CS_MASK 0x00400000
28
spi_cs_is_valid(unsigned int bus,unsigned int cs)29 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
30 {
31 return bus == 0 && cs == 0;
32 }
33
spi_cs_activate(struct spi_slave * slave)34 void spi_cs_activate(struct spi_slave *slave)
35 {
36 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
37
38 /* active low */
39 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
40 }
41
spi_cs_deactivate(struct spi_slave * slave)42 void spi_cs_deactivate(struct spi_slave *slave)
43 {
44 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
45
46 /* inactive high */
47 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
48 }
49 #endif /* CONFIG_MPC8XXX_SPI */
50
51 #ifdef CONFIG_FSL_ESDHC
board_mmc_init(bd_t * bd)52 int board_mmc_init(bd_t *bd)
53 {
54 return fsl_esdhc_mmc_init(bd);
55 }
56 #endif
57
read_board_info(void)58 static u8 read_board_info(void)
59 {
60 u8 val8;
61 i2c_set_bus_num(0);
62
63 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
64 return val8;
65 else
66 return 0;
67 }
68
checkboard(void)69 int checkboard(void)
70 {
71 static const char * const rev_str[] = {
72 "1.0",
73 "<reserved>",
74 "<reserved>",
75 "<reserved>",
76 "<unknown>",
77 };
78 u8 info;
79 int i;
80
81 info = read_board_info();
82 i = (!info) ? 4 : info & 0x03;
83
84 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
85
86 return 0;
87 }
88
89 static struct pci_region pcie_regions_0[] = {
90 {
91 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
92 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
93 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
94 .flags = PCI_REGION_MEM,
95 },
96 {
97 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
98 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
99 .size = CONFIG_SYS_PCIE1_IO_SIZE,
100 .flags = PCI_REGION_IO,
101 },
102 };
103
pci_init_board(void)104 void pci_init_board(void)
105 {
106 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
107 sysconf83xx_t *sysconf = &immr->sysconf;
108 law83xx_t *pcie_law = sysconf->pcielaw;
109 struct pci_region *pcie_reg[] = { pcie_regions_0 };
110
111 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
112 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
113
114 /* Deassert the resets in the control register */
115 out_be32(&sysconf->pecr1, 0xE0008000);
116 udelay(2000);
117
118 /* Configure PCI Express Local Access Windows */
119 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
120 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
121
122 mpc83xx_pcie_init(1, pcie_reg);
123 }
124 /*
125 * Miscellaneous late-boot configurations
126 *
127 * If a VSC7385 microcode image is present, then upload it.
128 */
misc_init_r(void)129 int misc_init_r(void)
130 {
131 #ifdef CONFIG_MPC8XXX_SPI
132 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
133 sysconf83xx_t *sysconf = &immr->sysconf;
134
135 /*
136 * Set proper bits in SICRH to allow SPI on header J8
137 *
138 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
139 * switch. The pinmux configuration does not have a fine enough
140 * granularity to support both simultaneously.
141 */
142 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
143 puts("WARNING: SPI enabled, TSEC2 support is broken\n");
144
145 /* Set header J8 SPI chip select output, disabled */
146 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
147 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
148 #endif
149
150 #ifdef CONFIG_VSC7385_IMAGE
151 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
152 CONFIG_VSC7385_IMAGE_SIZE)) {
153 puts("Failure uploading VSC7385 microcode.\n");
154 return 1;
155 }
156 #endif
157
158 return 0;
159 }
160 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)161 int ft_board_setup(void *blob, bd_t *bd)
162 {
163 ft_cpu_setup(blob, bd);
164 fsl_fdt_fixup_dr_usb(blob, bd);
165 fdt_fixup_esdhc(blob, bd);
166
167 return 0;
168 }
169 #endif
170
board_eth_init(bd_t * bis)171 int board_eth_init(bd_t *bis)
172 {
173 int rv, num_if = 0;
174
175 /* Initialize TSECs first */
176 rv = cpu_eth_init(bis);
177 if (rv >= 0)
178 num_if += rv;
179 else
180 printf("ERROR: failed to initialize TSECs.\n");
181
182 rv = pci_eth_init(bis);
183 if (rv >= 0)
184 num_if += rv;
185 else
186 printf("ERROR: failed to initialize PCI Ethernet.\n");
187
188 return num_if;
189 }
190