1 /* 2 * 3 * Common board functions for OMAP3 based boards. 4 * 5 * (C) Copyright 2004-2008 6 * Texas Instruments, <www.ti.com> 7 * 8 * Author : 9 * Sunil Kumar <sunilsaini05@gmail.com> 10 * Shashi Ranjan <shashiranjanmca05@gmail.com> 11 * 12 * Derived from Beagle Board and 3430 SDP code by 13 * Richard Woodruff <r-woodruff2@ti.com> 14 * Syed Mohammed Khasim <khasim@ti.com> 15 * 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 #include <common.h> 20 #include <dm.h> 21 #include <spl.h> 22 #include <asm/io.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mem.h> 25 #include <asm/cache.h> 26 #include <asm/armv7.h> 27 #include <asm/gpio.h> 28 #include <asm/omap_common.h> 29 #include <linux/compiler.h> 30 31 /* Declarations */ 32 extern omap3_sysinfo sysinfo; 33 #ifndef CONFIG_SYS_L2CACHE_OFF 34 static void omap3_invalidate_l2_cache_secure(void); 35 #endif 36 37 #ifdef CONFIG_DM_GPIO 38 static const struct omap_gpio_platdata omap34xx_gpio[] = { 39 { 0, OMAP34XX_GPIO1_BASE }, 40 { 1, OMAP34XX_GPIO2_BASE }, 41 { 2, OMAP34XX_GPIO3_BASE }, 42 { 3, OMAP34XX_GPIO4_BASE }, 43 { 4, OMAP34XX_GPIO5_BASE }, 44 { 5, OMAP34XX_GPIO6_BASE }, 45 }; 46 47 U_BOOT_DEVICES(omap34xx_gpios) = { 48 { "gpio_omap", &omap34xx_gpio[0] }, 49 { "gpio_omap", &omap34xx_gpio[1] }, 50 { "gpio_omap", &omap34xx_gpio[2] }, 51 { "gpio_omap", &omap34xx_gpio[3] }, 52 { "gpio_omap", &omap34xx_gpio[4] }, 53 { "gpio_omap", &omap34xx_gpio[5] }, 54 }; 55 56 #else 57 58 static const struct gpio_bank gpio_bank_34xx[6] = { 59 { (void *)OMAP34XX_GPIO1_BASE }, 60 { (void *)OMAP34XX_GPIO2_BASE }, 61 { (void *)OMAP34XX_GPIO3_BASE }, 62 { (void *)OMAP34XX_GPIO4_BASE }, 63 { (void *)OMAP34XX_GPIO5_BASE }, 64 { (void *)OMAP34XX_GPIO6_BASE }, 65 }; 66 67 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; 68 69 #endif 70 71 /****************************************************************************** 72 * Routine: secure_unlock 73 * Description: Setup security registers for access 74 * (GP Device only) 75 *****************************************************************************/ 76 void secure_unlock_mem(void) 77 { 78 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; 79 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; 80 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; 81 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; 82 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE; 83 84 /* Protection Module Register Target APE (PM_RT) */ 85 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); 86 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); 87 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); 88 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); 89 90 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); 91 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); 92 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); 93 94 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); 95 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); 96 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); 97 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2); 98 99 /* IVA Changes */ 100 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); 101 writel(UNLOCK_3, &pm_iva2_base->read_permission_0); 102 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0); 103 104 /* SDRC region 0 public */ 105 writel(UNLOCK_1, &sms_base->rg_att0); 106 } 107 108 /****************************************************************************** 109 * Routine: secureworld_exit() 110 * Description: If chip is EMU and boot type is external 111 * configure secure registers and exit secure world 112 * general use. 113 *****************************************************************************/ 114 void secureworld_exit(void) 115 { 116 unsigned long i; 117 118 /* configure non-secure access control register */ 119 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); 120 /* enabling co-processor CP10 and CP11 accesses in NS world */ 121 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); 122 /* 123 * allow allocation of locked TLBs and L2 lines in NS world 124 * allow use of PLE registers in NS world also 125 */ 126 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); 127 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); 128 129 /* Enable ASA in ACR register */ 130 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); 131 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); 132 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); 133 134 /* Exiting secure world */ 135 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); 136 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); 137 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); 138 } 139 140 /****************************************************************************** 141 * Routine: try_unlock_sram() 142 * Description: If chip is GP/EMU(special) type, unlock the SRAM for 143 * general use. 144 *****************************************************************************/ 145 void try_unlock_memory(void) 146 { 147 int mode; 148 int in_sdram = is_running_in_sdram(); 149 150 /* 151 * if GP device unlock device SRAM for general use 152 * secure code breaks for Secure/Emulation device - HS/E/T 153 */ 154 mode = get_device_type(); 155 if (mode == GP_DEVICE) 156 secure_unlock_mem(); 157 158 /* 159 * If device is EMU and boot is XIP external booting 160 * Unlock firewalls and disable L2 and put chip 161 * out of secure world 162 * 163 * Assuming memories are unlocked by the demon who put us in SDRAM 164 */ 165 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) 166 && (!in_sdram)) { 167 secure_unlock_mem(); 168 secureworld_exit(); 169 } 170 171 return; 172 } 173 174 void early_system_init(void) 175 { 176 hw_data_init(); 177 } 178 179 /****************************************************************************** 180 * Routine: s_init 181 * Description: Does early system init of muxing and clocks. 182 * - Called path is with SRAM stack. 183 *****************************************************************************/ 184 void s_init(void) 185 { 186 watchdog_init(); 187 early_system_init(); 188 189 try_unlock_memory(); 190 191 #ifndef CONFIG_SYS_L2CACHE_OFF 192 /* Invalidate L2-cache from secure mode */ 193 omap3_invalidate_l2_cache_secure(); 194 #endif 195 196 set_muxconf_regs(); 197 sdelay(100); 198 199 prcm_init(); 200 201 per_clocks_enable(); 202 203 #ifdef CONFIG_USB_EHCI_OMAP 204 ehci_clocks_enable(); 205 #endif 206 } 207 208 #ifdef CONFIG_SPL_BUILD 209 void board_init_f(ulong dummy) 210 { 211 early_system_init(); 212 mem_init(); 213 /* 214 * Save the boot parameters passed from romcode. 215 * We cannot delay the saving further than this, 216 * to prevent overwrites. 217 */ 218 save_omap_boot_params(); 219 } 220 #endif 221 222 /* 223 * Routine: misc_init_r 224 * Description: A basic misc_init_r that just displays the die ID 225 */ 226 int __weak misc_init_r(void) 227 { 228 omap_die_id_display(); 229 230 return 0; 231 } 232 233 /****************************************************************************** 234 * Routine: wait_for_command_complete 235 * Description: Wait for posting to finish on watchdog 236 *****************************************************************************/ 237 static void wait_for_command_complete(struct watchdog *wd_base) 238 { 239 int pending = 1; 240 do { 241 pending = readl(&wd_base->wwps); 242 } while (pending); 243 } 244 245 /****************************************************************************** 246 * Routine: watchdog_init 247 * Description: Shut down watch dogs 248 *****************************************************************************/ 249 void watchdog_init(void) 250 { 251 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; 252 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 253 254 /* 255 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is 256 * either taken care of by ROM (HS/EMU) or not accessible (GP). 257 * We need to take care of WD2-MPU or take a PRCM reset. WD3 258 * should not be running and does not generate a PRCM reset. 259 */ 260 261 setbits_le32(&prcm_base->fclken_wkup, 0x20); 262 setbits_le32(&prcm_base->iclken_wkup, 0x20); 263 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); 264 265 writel(WD_UNLOCK1, &wd2_base->wspr); 266 wait_for_command_complete(wd2_base); 267 writel(WD_UNLOCK2, &wd2_base->wspr); 268 } 269 270 /****************************************************************************** 271 * Dummy function to handle errors for EABI incompatibility 272 *****************************************************************************/ 273 void abort(void) 274 { 275 } 276 277 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) 278 /****************************************************************************** 279 * OMAP3 specific command to switch between NAND HW and SW ecc 280 *****************************************************************************/ 281 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 282 { 283 int hw, strength = 1; 284 285 if (argc < 2 || argc > 3) 286 goto usage; 287 288 if (strncmp(argv[1], "hw", 2) == 0) { 289 hw = 1; 290 if (argc == 3) { 291 if (strncmp(argv[2], "bch8", 4) == 0) 292 strength = 8; 293 else if (strncmp(argv[2], "bch16", 5) == 0) 294 strength = 16; 295 else if (strncmp(argv[2], "hamming", 7) != 0) 296 goto usage; 297 } 298 } else if (strncmp(argv[1], "sw", 2) == 0) { 299 hw = 0; 300 if (argc == 3) { 301 if (strncmp(argv[2], "bch8", 4) == 0) 302 strength = 8; 303 else if (strncmp(argv[2], "hamming", 7) != 0) 304 goto usage; 305 } 306 } else { 307 goto usage; 308 } 309 310 return -omap_nand_switch_ecc(hw, strength); 311 312 usage: 313 printf ("Usage: nandecc %s\n", cmdtp->usage); 314 return 1; 315 } 316 317 U_BOOT_CMD( 318 nandecc, 3, 1, do_switch_ecc, 319 "switch OMAP3 NAND ECC calculation algorithm", 320 "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming" 321 " and 8-bit/16-bit BCH\n" 322 " ecc calculation (second parameter may" 323 " be omitted).\n" 324 "nandecc sw - Switch to NAND software ecc algorithm." 325 ); 326 327 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ 328 329 #ifdef CONFIG_DISPLAY_BOARDINFO 330 /** 331 * Print board information 332 */ 333 int checkboard (void) 334 { 335 char *mem_s ; 336 337 if (is_mem_sdr()) 338 mem_s = "mSDR"; 339 else 340 mem_s = "LPDDR"; 341 342 printf("%s + %s/%s\n", sysinfo.board_string, mem_s, 343 sysinfo.nand_string); 344 345 return 0; 346 } 347 #endif /* CONFIG_DISPLAY_BOARDINFO */ 348 349 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) 350 { 351 u32 i, num_params = *parameters; 352 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; 353 354 /* 355 * copy the parameters to an un-cached area to avoid coherency 356 * issues 357 */ 358 for (i = 0; i < num_params; i++) { 359 __raw_writel(*parameters, sram_scratch_space); 360 parameters++; 361 sram_scratch_space++; 362 } 363 364 /* Now make the PPA call */ 365 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); 366 } 367 368 void __weak omap3_set_aux_cr_secure(u32 acr) 369 { 370 struct emu_hal_params emu_romcode_params; 371 372 emu_romcode_params.num_params = 1; 373 emu_romcode_params.param1 = acr; 374 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, 375 (u32 *)&emu_romcode_params); 376 } 377 378 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, 379 u32 cpu_rev_comb, u32 cpu_variant, 380 u32 cpu_rev) 381 { 382 if (get_device_type() == GP_DEVICE) 383 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl); 384 385 /* L2 Cache Auxiliary Control Register is not banked */ 386 } 387 388 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, 389 u32 cpu_variant, u32 cpu_rev) 390 { 391 /* Write ACR - affects secure banked bits */ 392 if (get_device_type() == GP_DEVICE) 393 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); 394 else 395 omap3_set_aux_cr_secure(acr); 396 397 /* Write ACR - affects non-secure banked bits - some erratas need it */ 398 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); 399 } 400 401 402 #ifndef CONFIG_SYS_L2CACHE_OFF 403 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) 404 { 405 u32 acr; 406 407 /* Read ACR */ 408 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 409 acr &= ~clear_bits; 410 acr |= set_bits; 411 v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); 412 413 } 414 415 /* Invalidate the entire L2 cache from secure mode */ 416 static void omap3_invalidate_l2_cache_secure(void) 417 { 418 if (get_device_type() == GP_DEVICE) { 419 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); 420 } else { 421 struct emu_hal_params emu_romcode_params; 422 emu_romcode_params.num_params = 1; 423 emu_romcode_params.param1 = 0; 424 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, 425 (u32 *)&emu_romcode_params); 426 } 427 } 428 429 void v7_outer_cache_enable(void) 430 { 431 432 /* 433 * Set L2EN 434 * On some revisions L2EN bit is banked on some revisions it's not 435 * No harm in setting both banked bits(in fact this is required 436 * by an erratum) 437 */ 438 omap3_update_aux_cr(0x2, 0); 439 } 440 441 void omap3_outer_cache_disable(void) 442 { 443 /* 444 * Clear L2EN 445 * On some revisions L2EN bit is banked on some revisions it's not 446 * No harm in clearing both banked bits(in fact this is required 447 * by an erratum) 448 */ 449 omap3_update_aux_cr(0, 0x2); 450 } 451 #endif /* !CONFIG_SYS_L2CACHE_OFF */ 452