1 /* 2 * Clock setup for SMDK5250 board based on EXYNOS5 3 * 4 * Copyright (C) 2012 Samsung Electronics 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <config.h> 11 #include <asm/io.h> 12 #include <asm/arch/clk.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/spl.h> 15 #include <asm/arch/dwmmc.h> 16 17 #include "clock_init.h" 18 #include "common_setup.h" 19 #include "exynos5_setup.h" 20 21 #define FSYS1_MMC0_DIV_MASK 0xff0f 22 #define FSYS1_MMC0_DIV_VAL 0x0701 23 24 struct arm_clk_ratios arm_clk_ratios[] = { 25 #ifdef CONFIG_EXYNOS5420 26 { 27 .arm_freq_mhz = 900, 28 29 .apll_mdiv = 0x96, 30 .apll_pdiv = 0x2, 31 .apll_sdiv = 0x1, 32 33 .arm2_ratio = 0x0, 34 .apll_ratio = 0x3, 35 .pclk_dbg_ratio = 0x6, 36 .atb_ratio = 0x6, 37 .periph_ratio = 0x7, 38 .acp_ratio = 0x0, 39 .cpud_ratio = 0x2, 40 .arm_ratio = 0x0, 41 } 42 #else 43 { 44 .arm_freq_mhz = 600, 45 46 .apll_mdiv = 0xc8, 47 .apll_pdiv = 0x4, 48 .apll_sdiv = 0x1, 49 50 .arm2_ratio = 0x0, 51 .apll_ratio = 0x1, 52 .pclk_dbg_ratio = 0x1, 53 .atb_ratio = 0x2, 54 .periph_ratio = 0x7, 55 .acp_ratio = 0x7, 56 .cpud_ratio = 0x1, 57 .arm_ratio = 0x0, 58 }, { 59 .arm_freq_mhz = 800, 60 61 .apll_mdiv = 0x64, 62 .apll_pdiv = 0x3, 63 .apll_sdiv = 0x0, 64 65 .arm2_ratio = 0x0, 66 .apll_ratio = 0x1, 67 .pclk_dbg_ratio = 0x1, 68 .atb_ratio = 0x3, 69 .periph_ratio = 0x7, 70 .acp_ratio = 0x7, 71 .cpud_ratio = 0x2, 72 .arm_ratio = 0x0, 73 }, { 74 .arm_freq_mhz = 1000, 75 76 .apll_mdiv = 0x7d, 77 .apll_pdiv = 0x3, 78 .apll_sdiv = 0x0, 79 80 .arm2_ratio = 0x0, 81 .apll_ratio = 0x1, 82 .pclk_dbg_ratio = 0x1, 83 .atb_ratio = 0x4, 84 .periph_ratio = 0x7, 85 .acp_ratio = 0x7, 86 .cpud_ratio = 0x2, 87 .arm_ratio = 0x0, 88 }, { 89 .arm_freq_mhz = 1200, 90 91 .apll_mdiv = 0x96, 92 .apll_pdiv = 0x3, 93 .apll_sdiv = 0x0, 94 95 .arm2_ratio = 0x0, 96 .apll_ratio = 0x3, 97 .pclk_dbg_ratio = 0x1, 98 .atb_ratio = 0x5, 99 .periph_ratio = 0x7, 100 .acp_ratio = 0x7, 101 .cpud_ratio = 0x3, 102 .arm_ratio = 0x0, 103 }, { 104 .arm_freq_mhz = 1400, 105 106 .apll_mdiv = 0xaf, 107 .apll_pdiv = 0x3, 108 .apll_sdiv = 0x0, 109 110 .arm2_ratio = 0x0, 111 .apll_ratio = 0x3, 112 .pclk_dbg_ratio = 0x1, 113 .atb_ratio = 0x6, 114 .periph_ratio = 0x7, 115 .acp_ratio = 0x7, 116 .cpud_ratio = 0x3, 117 .arm_ratio = 0x0, 118 }, { 119 .arm_freq_mhz = 1700, 120 121 .apll_mdiv = 0x1a9, 122 .apll_pdiv = 0x6, 123 .apll_sdiv = 0x0, 124 125 .arm2_ratio = 0x0, 126 .apll_ratio = 0x3, 127 .pclk_dbg_ratio = 0x1, 128 .atb_ratio = 0x6, 129 .periph_ratio = 0x7, 130 .acp_ratio = 0x7, 131 .cpud_ratio = 0x3, 132 .arm_ratio = 0x0, 133 } 134 #endif 135 }; 136 137 struct mem_timings mem_timings[] = { 138 #ifdef CONFIG_EXYNOS5420 139 { 140 .mem_manuf = MEM_MANUF_SAMSUNG, 141 .mem_type = DDR_MODE_DDR3, 142 .frequency_mhz = 800, 143 144 /* MPLL @800MHz*/ 145 .mpll_mdiv = 0xc8, 146 .mpll_pdiv = 0x3, 147 .mpll_sdiv = 0x1, 148 /* CPLL @666MHz */ 149 .cpll_mdiv = 0xde, 150 .cpll_pdiv = 0x4, 151 .cpll_sdiv = 0x1, 152 /* EPLL @600MHz */ 153 .epll_mdiv = 0x64, 154 .epll_pdiv = 0x2, 155 .epll_sdiv = 0x1, 156 /* VPLL @430MHz */ 157 .vpll_mdiv = 0xd7, 158 .vpll_pdiv = 0x3, 159 .vpll_sdiv = 0x2, 160 /* BPLL @800MHz */ 161 .bpll_mdiv = 0xc8, 162 .bpll_pdiv = 0x3, 163 .bpll_sdiv = 0x1, 164 /* KPLL @600MHz */ 165 .kpll_mdiv = 0x190, 166 .kpll_pdiv = 0x4, 167 .kpll_sdiv = 0x2, 168 /* DPLL @600MHz */ 169 .dpll_mdiv = 0x190, 170 .dpll_pdiv = 0x4, 171 .dpll_sdiv = 0x2, 172 /* IPLL @370MHz */ 173 .ipll_mdiv = 0xb9, 174 .ipll_pdiv = 0x3, 175 .ipll_sdiv = 0x2, 176 /* SPLL @400MHz */ 177 .spll_mdiv = 0xc8, 178 .spll_pdiv = 0x3, 179 .spll_sdiv = 0x2, 180 /* RPLL @141Mhz */ 181 .rpll_mdiv = 0x5E, 182 .rpll_pdiv = 0x2, 183 .rpll_sdiv = 0x3, 184 185 .direct_cmd_msr = { 186 0x00020018, 0x00030000, 0x00010046, 0x00000d70, 187 0x00000c70 188 }, 189 .timing_ref = 0x000000bb, 190 .timing_row = 0x6836650f, 191 .timing_data = 0x3630580b, 192 .timing_power = 0x41000a26, 193 .phy0_dqs = 0x08080808, 194 .phy1_dqs = 0x08080808, 195 .phy0_dq = 0x08080808, 196 .phy1_dq = 0x08080808, 197 .phy0_tFS = 0x8, 198 .phy1_tFS = 0x8, 199 .phy0_pulld_dqs = 0xf, 200 .phy1_pulld_dqs = 0xf, 201 202 .lpddr3_ctrl_phy_reset = 0x1, 203 .ctrl_start_point = 0x10, 204 .ctrl_inc = 0x10, 205 .ctrl_start = 0x1, 206 .ctrl_dll_on = 0x1, 207 .ctrl_ref = 0x8, 208 209 .ctrl_force = 0x1a, 210 .ctrl_rdlat = 0x0b, 211 .ctrl_bstlen = 0x08, 212 213 .fp_resync = 0x8, 214 .iv_size = 0x7, 215 .dfi_init_start = 1, 216 .aref_en = 1, 217 218 .rd_fetch = 0x3, 219 220 .zq_mode_dds = 0x7, 221 .zq_mode_term = 0x1, 222 .zq_mode_noterm = 1, 223 224 /* 225 * Dynamic Clock: Always Running 226 * Memory Burst length: 8 227 * Number of chips: 1 228 * Memory Bus width: 32 bit 229 * Memory Type: DDR3 230 * Additional Latancy for PLL: 0 Cycle 231 */ 232 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | 233 DMC_MEMCONTROL_DPWRDN_DISABLE | 234 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | 235 DMC_MEMCONTROL_TP_DISABLE | 236 DMC_MEMCONTROL_DSREF_DISABLE | 237 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | 238 DMC_MEMCONTROL_MEM_TYPE_DDR3 | 239 DMC_MEMCONTROL_MEM_WIDTH_32BIT | 240 DMC_MEMCONTROL_NUM_CHIP_1 | 241 DMC_MEMCONTROL_BL_8 | 242 DMC_MEMCONTROL_PZQ_DISABLE | 243 DMC_MEMCONTROL_MRR_BYTE_7_0, 244 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | 245 DMC_MEMCONFIGX_CHIP_COL_10 | 246 DMC_MEMCONFIGX_CHIP_ROW_15 | 247 DMC_MEMCONFIGX_CHIP_BANK_8, 248 .prechconfig_tp_cnt = 0xff, 249 .dpwrdn_cyc = 0xff, 250 .dsref_cyc = 0xffff, 251 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | 252 DMC_CONCONTROL_TIMEOUT_LEVEL0 | 253 DMC_CONCONTROL_RD_FETCH_DISABLE | 254 DMC_CONCONTROL_EMPTY_DISABLE | 255 DMC_CONCONTROL_AREF_EN_DISABLE | 256 DMC_CONCONTROL_IO_PD_CON_DISABLE, 257 .dmc_channels = 1, 258 .chips_per_channel = 1, 259 .chips_to_configure = 1, 260 .send_zq_init = 1, 261 .gate_leveling_enable = 1, 262 .read_leveling_enable = 0, 263 } 264 #else 265 { 266 .mem_manuf = MEM_MANUF_ELPIDA, 267 .mem_type = DDR_MODE_DDR3, 268 .frequency_mhz = 800, 269 .mpll_mdiv = 0xc8, 270 .mpll_pdiv = 0x3, 271 .mpll_sdiv = 0x0, 272 .cpll_mdiv = 0xde, 273 .cpll_pdiv = 0x4, 274 .cpll_sdiv = 0x2, 275 .gpll_mdiv = 0x215, 276 .gpll_pdiv = 0xc, 277 .gpll_sdiv = 0x1, 278 .epll_mdiv = 0x60, 279 .epll_pdiv = 0x3, 280 .epll_sdiv = 0x3, 281 .vpll_mdiv = 0x96, 282 .vpll_pdiv = 0x3, 283 .vpll_sdiv = 0x2, 284 285 .bpll_mdiv = 0x64, 286 .bpll_pdiv = 0x3, 287 .bpll_sdiv = 0x0, 288 .pclk_cdrex_ratio = 0x5, 289 .direct_cmd_msr = { 290 0x00020018, 0x00030000, 0x00010042, 0x00000d70 291 }, 292 .timing_ref = 0x000000bb, 293 .timing_row = 0x8c36650e, 294 .timing_data = 0x3630580b, 295 .timing_power = 0x41000a44, 296 .phy0_dqs = 0x08080808, 297 .phy1_dqs = 0x08080808, 298 .phy0_dq = 0x08080808, 299 .phy1_dq = 0x08080808, 300 .phy0_tFS = 0x4, 301 .phy1_tFS = 0x4, 302 .phy0_pulld_dqs = 0xf, 303 .phy1_pulld_dqs = 0xf, 304 305 .lpddr3_ctrl_phy_reset = 0x1, 306 .ctrl_start_point = 0x10, 307 .ctrl_inc = 0x10, 308 .ctrl_start = 0x1, 309 .ctrl_dll_on = 0x1, 310 .ctrl_ref = 0x8, 311 312 .ctrl_force = 0x1a, 313 .ctrl_rdlat = 0x0b, 314 .ctrl_bstlen = 0x08, 315 316 .fp_resync = 0x8, 317 .iv_size = 0x7, 318 .dfi_init_start = 1, 319 .aref_en = 1, 320 321 .rd_fetch = 0x3, 322 323 .zq_mode_dds = 0x7, 324 .zq_mode_term = 0x1, 325 .zq_mode_noterm = 0, 326 327 /* 328 * Dynamic Clock: Always Running 329 * Memory Burst length: 8 330 * Number of chips: 1 331 * Memory Bus width: 32 bit 332 * Memory Type: DDR3 333 * Additional Latancy for PLL: 0 Cycle 334 */ 335 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | 336 DMC_MEMCONTROL_DPWRDN_DISABLE | 337 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | 338 DMC_MEMCONTROL_TP_DISABLE | 339 DMC_MEMCONTROL_DSREF_ENABLE | 340 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | 341 DMC_MEMCONTROL_MEM_TYPE_DDR3 | 342 DMC_MEMCONTROL_MEM_WIDTH_32BIT | 343 DMC_MEMCONTROL_NUM_CHIP_1 | 344 DMC_MEMCONTROL_BL_8 | 345 DMC_MEMCONTROL_PZQ_DISABLE | 346 DMC_MEMCONTROL_MRR_BYTE_7_0, 347 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED | 348 DMC_MEMCONFIGX_CHIP_COL_10 | 349 DMC_MEMCONFIGX_CHIP_ROW_15 | 350 DMC_MEMCONFIGX_CHIP_BANK_8, 351 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), 352 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), 353 .prechconfig_tp_cnt = 0xff, 354 .dpwrdn_cyc = 0xff, 355 .dsref_cyc = 0xffff, 356 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | 357 DMC_CONCONTROL_TIMEOUT_LEVEL0 | 358 DMC_CONCONTROL_RD_FETCH_DISABLE | 359 DMC_CONCONTROL_EMPTY_DISABLE | 360 DMC_CONCONTROL_AREF_EN_DISABLE | 361 DMC_CONCONTROL_IO_PD_CON_DISABLE, 362 .dmc_channels = 2, 363 .chips_per_channel = 2, 364 .chips_to_configure = 1, 365 .send_zq_init = 1, 366 .impedance = IMP_OUTPUT_DRV_30_OHM, 367 .gate_leveling_enable = 0, 368 }, { 369 .mem_manuf = MEM_MANUF_SAMSUNG, 370 .mem_type = DDR_MODE_DDR3, 371 .frequency_mhz = 800, 372 .mpll_mdiv = 0xc8, 373 .mpll_pdiv = 0x3, 374 .mpll_sdiv = 0x0, 375 .cpll_mdiv = 0xde, 376 .cpll_pdiv = 0x4, 377 .cpll_sdiv = 0x2, 378 .gpll_mdiv = 0x215, 379 .gpll_pdiv = 0xc, 380 .gpll_sdiv = 0x1, 381 .epll_mdiv = 0x60, 382 .epll_pdiv = 0x3, 383 .epll_sdiv = 0x3, 384 .vpll_mdiv = 0x96, 385 .vpll_pdiv = 0x3, 386 .vpll_sdiv = 0x2, 387 388 .bpll_mdiv = 0x64, 389 .bpll_pdiv = 0x3, 390 .bpll_sdiv = 0x0, 391 .pclk_cdrex_ratio = 0x5, 392 .direct_cmd_msr = { 393 0x00020018, 0x00030000, 0x00010000, 0x00000d70 394 }, 395 .timing_ref = 0x000000bb, 396 .timing_row = 0x8c36650e, 397 .timing_data = 0x3630580b, 398 .timing_power = 0x41000a44, 399 .phy0_dqs = 0x08080808, 400 .phy1_dqs = 0x08080808, 401 .phy0_dq = 0x08080808, 402 .phy1_dq = 0x08080808, 403 .phy0_tFS = 0x8, 404 .phy1_tFS = 0x8, 405 .phy0_pulld_dqs = 0xf, 406 .phy1_pulld_dqs = 0xf, 407 408 .lpddr3_ctrl_phy_reset = 0x1, 409 .ctrl_start_point = 0x10, 410 .ctrl_inc = 0x10, 411 .ctrl_start = 0x1, 412 .ctrl_dll_on = 0x1, 413 .ctrl_ref = 0x8, 414 415 .ctrl_force = 0x1a, 416 .ctrl_rdlat = 0x0b, 417 .ctrl_bstlen = 0x08, 418 419 .fp_resync = 0x8, 420 .iv_size = 0x7, 421 .dfi_init_start = 1, 422 .aref_en = 1, 423 424 .rd_fetch = 0x3, 425 426 .zq_mode_dds = 0x5, 427 .zq_mode_term = 0x1, 428 .zq_mode_noterm = 1, 429 430 /* 431 * Dynamic Clock: Always Running 432 * Memory Burst length: 8 433 * Number of chips: 1 434 * Memory Bus width: 32 bit 435 * Memory Type: DDR3 436 * Additional Latancy for PLL: 0 Cycle 437 */ 438 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | 439 DMC_MEMCONTROL_DPWRDN_DISABLE | 440 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | 441 DMC_MEMCONTROL_TP_DISABLE | 442 DMC_MEMCONTROL_DSREF_ENABLE | 443 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | 444 DMC_MEMCONTROL_MEM_TYPE_DDR3 | 445 DMC_MEMCONTROL_MEM_WIDTH_32BIT | 446 DMC_MEMCONTROL_NUM_CHIP_1 | 447 DMC_MEMCONTROL_BL_8 | 448 DMC_MEMCONTROL_PZQ_DISABLE | 449 DMC_MEMCONTROL_MRR_BYTE_7_0, 450 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED | 451 DMC_MEMCONFIGX_CHIP_COL_10 | 452 DMC_MEMCONFIGX_CHIP_ROW_15 | 453 DMC_MEMCONFIGX_CHIP_BANK_8, 454 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), 455 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), 456 .prechconfig_tp_cnt = 0xff, 457 .dpwrdn_cyc = 0xff, 458 .dsref_cyc = 0xffff, 459 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | 460 DMC_CONCONTROL_TIMEOUT_LEVEL0 | 461 DMC_CONCONTROL_RD_FETCH_DISABLE | 462 DMC_CONCONTROL_EMPTY_DISABLE | 463 DMC_CONCONTROL_AREF_EN_DISABLE | 464 DMC_CONCONTROL_IO_PD_CON_DISABLE, 465 .dmc_channels = 2, 466 .chips_per_channel = 2, 467 .chips_to_configure = 1, 468 .send_zq_init = 1, 469 .impedance = IMP_OUTPUT_DRV_40_OHM, 470 .gate_leveling_enable = 1, 471 } 472 #endif 473 }; 474 475 /** 476 * Get the required memory type and speed (SPL version). 477 * 478 * In SPL we have no device tree, so we use the machine parameters 479 * 480 * @param mem_type Returns memory type 481 * @param frequency_mhz Returns memory speed in MHz 482 * @param arm_freq Returns ARM clock speed in MHz 483 * @param mem_manuf Return Memory Manufacturer name 484 */ 485 static void clock_get_mem_selection(enum ddr_mode *mem_type, 486 unsigned *frequency_mhz, unsigned *arm_freq, 487 enum mem_manuf *mem_manuf) 488 { 489 struct spl_machine_param *params; 490 491 params = spl_get_machine_params(); 492 *mem_type = params->mem_type; 493 *frequency_mhz = params->frequency_mhz; 494 *arm_freq = params->arm_freq_mhz; 495 *mem_manuf = params->mem_manuf; 496 } 497 498 /* Get the ratios for setting ARM clock */ 499 struct arm_clk_ratios *get_arm_ratios(void) 500 { 501 struct arm_clk_ratios *arm_ratio; 502 enum ddr_mode mem_type; 503 enum mem_manuf mem_manuf; 504 unsigned frequency_mhz, arm_freq; 505 int i; 506 507 clock_get_mem_selection(&mem_type, &frequency_mhz, 508 &arm_freq, &mem_manuf); 509 510 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); 511 i++, arm_ratio++) { 512 if (arm_ratio->arm_freq_mhz == arm_freq) 513 return arm_ratio; 514 } 515 516 /* will hang if failed to find clock ratio */ 517 while (1) 518 ; 519 520 return NULL; 521 } 522 523 struct mem_timings *clock_get_mem_timings(void) 524 { 525 struct mem_timings *mem; 526 enum ddr_mode mem_type; 527 enum mem_manuf mem_manuf; 528 unsigned frequency_mhz, arm_freq; 529 int i; 530 531 clock_get_mem_selection(&mem_type, &frequency_mhz, 532 &arm_freq, &mem_manuf); 533 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); 534 i++, mem++) { 535 if (mem->mem_type == mem_type && 536 mem->frequency_mhz == frequency_mhz && 537 mem->mem_manuf == mem_manuf) 538 return mem; 539 } 540 541 /* will hang if failed to find memory timings */ 542 while (1) 543 ; 544 545 return NULL; 546 } 547 548 static void exynos5250_system_clock_init(void) 549 { 550 struct exynos5_clock *clk = 551 (struct exynos5_clock *)samsung_get_base_clock(); 552 struct mem_timings *mem; 553 struct arm_clk_ratios *arm_clk_ratio; 554 u32 val, tmp; 555 556 mem = clock_get_mem_timings(); 557 arm_clk_ratio = get_arm_ratios(); 558 559 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); 560 do { 561 val = readl(&clk->mux_stat_cpu); 562 } while ((val | MUX_APLL_SEL_MASK) != val); 563 564 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); 565 do { 566 val = readl(&clk->mux_stat_core1); 567 } while ((val | MUX_MPLL_SEL_MASK) != val); 568 569 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); 570 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); 571 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); 572 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); 573 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK 574 | MUX_GPLL_SEL_MASK; 575 do { 576 val = readl(&clk->mux_stat_top2); 577 } while ((val | tmp) != val); 578 579 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); 580 do { 581 val = readl(&clk->mux_stat_cdrex); 582 } while ((val | MUX_BPLL_SEL_MASK) != val); 583 584 /* PLL locktime */ 585 writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); 586 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); 587 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); 588 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); 589 writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock); 590 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); 591 writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock); 592 593 writel(CLK_REG_DISABLE, &clk->pll_div2_sel); 594 595 writel(MUX_HPM_SEL_MASK, &clk->src_cpu); 596 do { 597 val = readl(&clk->mux_stat_cpu); 598 } while ((val | HPM_SEL_SCLK_MPLL) != val); 599 600 val = arm_clk_ratio->arm2_ratio << 28 601 | arm_clk_ratio->apll_ratio << 24 602 | arm_clk_ratio->pclk_dbg_ratio << 20 603 | arm_clk_ratio->atb_ratio << 16 604 | arm_clk_ratio->periph_ratio << 12 605 | arm_clk_ratio->acp_ratio << 8 606 | arm_clk_ratio->cpud_ratio << 4 607 | arm_clk_ratio->arm_ratio; 608 writel(val, &clk->div_cpu0); 609 do { 610 val = readl(&clk->div_stat_cpu0); 611 } while (0 != val); 612 613 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); 614 do { 615 val = readl(&clk->div_stat_cpu1); 616 } while (0 != val); 617 618 /* Set APLL */ 619 writel(APLL_CON1_VAL, &clk->apll_con1); 620 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, 621 arm_clk_ratio->apll_sdiv); 622 writel(val, &clk->apll_con0); 623 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) 624 ; 625 626 /* Set MPLL */ 627 writel(MPLL_CON1_VAL, &clk->mpll_con1); 628 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); 629 writel(val, &clk->mpll_con0); 630 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) 631 ; 632 633 /* Set BPLL */ 634 writel(BPLL_CON1_VAL, &clk->bpll_con1); 635 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); 636 writel(val, &clk->bpll_con0); 637 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) 638 ; 639 640 /* Set CPLL */ 641 writel(CPLL_CON1_VAL, &clk->cpll_con1); 642 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); 643 writel(val, &clk->cpll_con0); 644 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) 645 ; 646 647 /* Set GPLL */ 648 writel(GPLL_CON1_VAL, &clk->gpll_con1); 649 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); 650 writel(val, &clk->gpll_con0); 651 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) 652 ; 653 654 /* Set EPLL */ 655 writel(EPLL_CON2_VAL, &clk->epll_con2); 656 writel(EPLL_CON1_VAL, &clk->epll_con1); 657 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); 658 writel(val, &clk->epll_con0); 659 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) 660 ; 661 662 /* Set VPLL */ 663 writel(VPLL_CON2_VAL, &clk->vpll_con2); 664 writel(VPLL_CON1_VAL, &clk->vpll_con1); 665 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); 666 writel(val, &clk->vpll_con0); 667 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) 668 ; 669 670 writel(CLK_SRC_CORE0_VAL, &clk->src_core0); 671 writel(CLK_DIV_CORE0_VAL, &clk->div_core0); 672 while (readl(&clk->div_stat_core0) != 0) 673 ; 674 675 writel(CLK_DIV_CORE1_VAL, &clk->div_core1); 676 while (readl(&clk->div_stat_core1) != 0) 677 ; 678 679 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); 680 while (readl(&clk->div_stat_sysrgt) != 0) 681 ; 682 683 writel(CLK_DIV_ACP_VAL, &clk->div_acp); 684 while (readl(&clk->div_stat_acp) != 0) 685 ; 686 687 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); 688 while (readl(&clk->div_stat_syslft) != 0) 689 ; 690 691 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); 692 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); 693 writel(TOP2_VAL, &clk->src_top2); 694 writel(CLK_SRC_TOP3_VAL, &clk->src_top3); 695 696 writel(CLK_DIV_TOP0_VAL, &clk->div_top0); 697 while (readl(&clk->div_stat_top0)) 698 ; 699 700 writel(CLK_DIV_TOP1_VAL, &clk->div_top1); 701 while (readl(&clk->div_stat_top1)) 702 ; 703 704 writel(CLK_SRC_LEX_VAL, &clk->src_lex); 705 while (1) { 706 val = readl(&clk->mux_stat_lex); 707 if (val == (val | 1)) 708 break; 709 } 710 711 writel(CLK_DIV_LEX_VAL, &clk->div_lex); 712 while (readl(&clk->div_stat_lex)) 713 ; 714 715 writel(CLK_DIV_R0X_VAL, &clk->div_r0x); 716 while (readl(&clk->div_stat_r0x)) 717 ; 718 719 writel(CLK_DIV_R0X_VAL, &clk->div_r0x); 720 while (readl(&clk->div_stat_r0x)) 721 ; 722 723 writel(CLK_DIV_R1X_VAL, &clk->div_r1x); 724 while (readl(&clk->div_stat_r1x)) 725 ; 726 727 writel(CLK_REG_DISABLE, &clk->src_cdrex); 728 729 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); 730 while (readl(&clk->div_stat_cdrex)) 731 ; 732 733 val = readl(&clk->src_cpu); 734 val |= CLK_SRC_CPU_VAL; 735 writel(val, &clk->src_cpu); 736 737 val = readl(&clk->src_top2); 738 val |= CLK_SRC_TOP2_VAL; 739 writel(val, &clk->src_top2); 740 741 val = readl(&clk->src_core1); 742 val |= CLK_SRC_CORE1_VAL; 743 writel(val, &clk->src_core1); 744 745 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); 746 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); 747 while (readl(&clk->div_stat_fsys0)) 748 ; 749 750 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); 751 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); 752 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); 753 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); 754 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); 755 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); 756 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); 757 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); 758 759 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); 760 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); 761 762 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); 763 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); 764 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); 765 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); 766 767 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); 768 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); 769 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); 770 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); 771 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); 772 773 /* FIMD1 SRC CLK SELECTION */ 774 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); 775 776 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET 777 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET 778 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET 779 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; 780 writel(val, &clk->div_fsys2); 781 } 782 783 static void exynos5420_system_clock_init(void) 784 { 785 struct exynos5420_clock *clk = 786 (struct exynos5420_clock *)samsung_get_base_clock(); 787 struct mem_timings *mem; 788 struct arm_clk_ratios *arm_clk_ratio; 789 u32 val; 790 791 mem = clock_get_mem_timings(); 792 arm_clk_ratio = get_arm_ratios(); 793 794 /* PLL locktime */ 795 writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); 796 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); 797 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); 798 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); 799 writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock); 800 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); 801 writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock); 802 writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); 803 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); 804 writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); 805 writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock); 806 807 setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK); 808 809 writel(0, &clk->src_top6); 810 811 writel(0, &clk->src_cdrex); 812 writel(SRC_KFC_HPM_SEL, &clk->src_kfc); 813 writel(HPM_RATIO, &clk->div_cpu1); 814 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); 815 816 /* switch A15 clock source to OSC clock before changing APLL */ 817 clrbits_le32(&clk->src_cpu, APLL_FOUT); 818 819 /* Set APLL */ 820 writel(APLL_CON1_VAL, &clk->apll_con1); 821 val = set_pll(arm_clk_ratio->apll_mdiv, 822 arm_clk_ratio->apll_pdiv, 823 arm_clk_ratio->apll_sdiv); 824 writel(val, &clk->apll_con0); 825 while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) 826 ; 827 828 /* now it is safe to switch to APLL */ 829 setbits_le32(&clk->src_cpu, APLL_FOUT); 830 831 writel(SRC_KFC_HPM_SEL, &clk->src_kfc); 832 writel(CLK_DIV_KFC_VAL, &clk->div_kfc0); 833 834 /* switch A7 clock source to OSC clock before changing KPLL */ 835 clrbits_le32(&clk->src_kfc, KPLL_FOUT); 836 837 /* Set KPLL*/ 838 writel(KPLL_CON1_VAL, &clk->kpll_con1); 839 val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv); 840 writel(val, &clk->kpll_con0); 841 while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) 842 ; 843 844 /* now it is safe to switch to KPLL */ 845 setbits_le32(&clk->src_kfc, KPLL_FOUT); 846 847 /* Set MPLL */ 848 writel(MPLL_CON1_VAL, &clk->mpll_con1); 849 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); 850 writel(val, &clk->mpll_con0); 851 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) 852 ; 853 854 /* Set DPLL */ 855 writel(DPLL_CON1_VAL, &clk->dpll_con1); 856 val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv); 857 writel(val, &clk->dpll_con0); 858 while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0) 859 ; 860 861 /* Set EPLL */ 862 writel(EPLL_CON2_VAL, &clk->epll_con2); 863 writel(EPLL_CON1_VAL, &clk->epll_con1); 864 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); 865 writel(val, &clk->epll_con0); 866 while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0) 867 ; 868 869 /* Set CPLL */ 870 writel(CPLL_CON1_VAL, &clk->cpll_con1); 871 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); 872 writel(val, &clk->cpll_con0); 873 while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) 874 ; 875 876 /* Set IPLL */ 877 writel(IPLL_CON1_VAL, &clk->ipll_con1); 878 val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv); 879 writel(val, &clk->ipll_con0); 880 while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0) 881 ; 882 883 /* Set VPLL */ 884 writel(VPLL_CON1_VAL, &clk->vpll_con1); 885 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); 886 writel(val, &clk->vpll_con0); 887 while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0) 888 ; 889 890 /* Set BPLL */ 891 writel(BPLL_CON1_VAL, &clk->bpll_con1); 892 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); 893 writel(val, &clk->bpll_con0); 894 while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0) 895 ; 896 897 /* Set SPLL */ 898 writel(SPLL_CON1_VAL, &clk->spll_con1); 899 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv); 900 writel(val, &clk->spll_con0); 901 while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) 902 ; 903 904 /* Set RPLL */ 905 writel(RPLL_CON2_VAL, &clk->rpll_con2); 906 writel(RPLL_CON1_VAL, &clk->rpll_con1); 907 val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); 908 writel(val, &clk->rpll_con0); 909 while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) 910 ; 911 912 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); 913 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1); 914 915 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); 916 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); 917 writel(CLK_SRC_TOP2_VAL, &clk->src_top2); 918 writel(CLK_SRC_TOP7_VAL, &clk->src_top7); 919 920 writel(CLK_DIV_TOP0_VAL, &clk->div_top0); 921 writel(CLK_DIV_TOP1_VAL, &clk->div_top1); 922 writel(CLK_DIV_TOP2_VAL, &clk->div_top2); 923 924 writel(0, &clk->src_top10); 925 writel(0, &clk->src_top11); 926 writel(0, &clk->src_top12); 927 928 writel(CLK_SRC_TOP3_VAL, &clk->src_top3); 929 writel(CLK_SRC_TOP4_VAL, &clk->src_top4); 930 writel(CLK_SRC_TOP5_VAL, &clk->src_top5); 931 932 /* DISP1 BLK CLK SELECTION */ 933 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10); 934 writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10); 935 936 /* AUDIO BLK */ 937 writel(AUDIO0_SEL_EPLL, &clk->src_mau); 938 writel(DIV_MAU_VAL, &clk->div_mau); 939 940 /* FSYS */ 941 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); 942 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); 943 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); 944 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); 945 946 writel(CLK_SRC_ISP_VAL, &clk->src_isp); 947 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); 948 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); 949 950 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); 951 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); 952 953 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); 954 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); 955 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); 956 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); 957 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4); 958 959 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1); 960 961 writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio); 962 writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio); 963 writel(CLK_DIV_G2D, &clk->div_g2d); 964 965 writel(CLK_SRC_TOP6_VAL, &clk->src_top6); 966 writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex); 967 writel(CLK_SRC_KFC_VAL, &clk->src_kfc); 968 } 969 970 void system_clock_init(void) 971 { 972 if (proid_is_exynos5420() || proid_is_exynos5422()) 973 exynos5420_system_clock_init(); 974 else 975 exynos5250_system_clock_init(); 976 } 977 978 void clock_init_dp_clock(void) 979 { 980 struct exynos5_clock *clk = 981 (struct exynos5_clock *)samsung_get_base_clock(); 982 983 /* DP clock enable */ 984 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); 985 986 /* We run DP at 267 Mhz */ 987 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); 988 } 989 990 /* 991 * Set clock divisor value for booting from EMMC. 992 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. 993 */ 994 void emmc_boot_clk_div_set(void) 995 { 996 struct exynos5_clock *clk = 997 (struct exynos5_clock *)samsung_get_base_clock(); 998 unsigned int div_mmc; 999 1000 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; 1001 div_mmc |= FSYS1_MMC0_DIV_VAL; 1002 writel(div_mmc, (unsigned int) &clk->div_fsys1); 1003 } 1004