1 /* 2 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <linux/libfdt.h> 11 #include <asm/io.h> 12 #include <asm/system.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include <asm/armv8/mmu.h> 16 17 /* Armada 7k/8k */ 18 #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000)) 19 #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84) 20 #define RFU_SW_RESET_OFFSET 0 21 22 /* 23 * The following table includes all memory regions for Armada 7k and 24 * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets 25 * define these regions at the beginning of the struct so that they 26 * can be easier removed later dynamically if an Armada 7k device is detected. 27 * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt 28 */ 29 #define ARMADA_7K8K_COMMON_REGIONS_START 2 30 static struct mm_region mvebu_mem_map[] = { 31 /* Armada 80x0 memory regions include the CP1 (slave) units */ 32 { 33 /* SRAM, MMIO regions - CP110 slave region */ 34 .phys = 0xf4000000UL, 35 .virt = 0xf4000000UL, 36 .size = 0x02000000UL, /* 32MiB internal registers */ 37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 38 PTE_BLOCK_NON_SHARE 39 }, 40 { 41 /* PCI CP1 regions */ 42 .phys = 0xfa000000UL, 43 .virt = 0xfa000000UL, 44 .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */ 45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 46 PTE_BLOCK_NON_SHARE 47 }, 48 /* Armada 80x0 and 70x0 common memory regions start here */ 49 { 50 /* RAM */ 51 .phys = 0x0UL, 52 .virt = 0x0UL, 53 .size = 0x80000000UL, 54 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 55 PTE_BLOCK_INNER_SHARE 56 }, 57 { 58 /* SRAM, MMIO regions - AP806 region */ 59 .phys = 0xf0000000UL, 60 .virt = 0xf0000000UL, 61 .size = 0x01000000UL, /* 16MiB internal registers */ 62 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 63 PTE_BLOCK_NON_SHARE 64 }, 65 { 66 /* SRAM, MMIO regions - CP110 master region */ 67 .phys = 0xf2000000UL, 68 .virt = 0xf2000000UL, 69 .size = 0x02000000UL, /* 32MiB internal registers */ 70 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 71 PTE_BLOCK_NON_SHARE 72 }, 73 { 74 /* PCI CP0 regions */ 75 .phys = 0xf6000000UL, 76 .virt = 0xf6000000UL, 77 .size = 0x04000000UL, /* 64MiB CP110 master PCI space */ 78 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 79 PTE_BLOCK_NON_SHARE 80 }, 81 { 82 0, 83 } 84 }; 85 86 struct mm_region *mem_map = mvebu_mem_map; 87 88 void enable_caches(void) 89 { 90 /* 91 * Armada 7k is not equipped with the CP110 slave CP. In case this 92 * code runs on an Armada 7k device, lets remove the CP110 slave 93 * entries from the memory mapping by moving the start to the 94 * common regions. 95 */ 96 if (of_machine_is_compatible("marvell,armada7040")) 97 mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START]; 98 99 icache_enable(); 100 dcache_enable(); 101 } 102 103 void reset_cpu(ulong ignored) 104 { 105 u32 reg; 106 107 reg = readl(RFU_GLOBAL_SW_RST); 108 reg &= ~(1 << RFU_SW_RESET_OFFSET); 109 writel(reg, RFU_GLOBAL_SW_RST); 110 } 111 112 /* 113 * TODO - implement this functionality using platform 114 * clock driver once it gets available 115 * Return NAND clock in Hz 116 */ 117 u32 mvebu_get_nand_clock(void) 118 { 119 unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL; 120 unsigned long NF_CLOCK_SEL_MASK = 0x1; 121 u32 reg; 122 123 reg = readl(NAND_FLASH_CLK_CTRL); 124 if (reg & NF_CLOCK_SEL_MASK) 125 return 400 * 1000000; 126 else 127 return 250 * 1000000; 128 } 129