1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * Based on Atheros LSDK/QSDK 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/addrspace.h> 11 #include <asm/types.h> 12 #include <mach/ar71xx_regs.h> 13 #include <mach/ath79.h> 14 15 #define DDR_CTRL_UPD_EMR3S BIT(5) 16 #define DDR_CTRL_UPD_EMR2S BIT(4) 17 #define DDR_CTRL_PRECHARGE BIT(3) 18 #define DDR_CTRL_AUTO_REFRESH BIT(2) 19 #define DDR_CTRL_UPD_EMRS BIT(1) 20 #define DDR_CTRL_UPD_MRS BIT(0) 21 22 #define DDR_REFRESH_EN BIT(14) 23 #define DDR_REFRESH_M 0x3ff 24 #define DDR_REFRESH(x) ((x) & DDR_REFRESH_M) 25 #define DDR_REFRESH_VAL (DDR_REFRESH_EN | DDR_REFRESH(312)) 26 27 #define DDR_TRAS_S 0 28 #define DDR_TRAS_M 0x1f 29 #define DDR_TRAS(x) (((x) & DDR_TRAS_M) << DDR_TRAS_S) 30 #define DDR_TRCD_M 0xf 31 #define DDR_TRCD_S 5 32 #define DDR_TRCD(x) (((x) & DDR_TRCD_M) << DDR_TRCD_S) 33 #define DDR_TRP_M 0xf 34 #define DDR_TRP_S 9 35 #define DDR_TRP(x) (((x) & DDR_TRP_M) << DDR_TRP_S) 36 #define DDR_TRRD_M 0xf 37 #define DDR_TRRD_S 13 38 #define DDR_TRRD(x) (((x) & DDR_TRRD_M) << DDR_TRRD_S) 39 #define DDR_TRFC_M 0x7f 40 #define DDR_TRFC_S 17 41 #define DDR_TRFC(x) (((x) & DDR_TRFC_M) << DDR_TRFC_S) 42 #define DDR_TMRD_M 0xf 43 #define DDR_TMRD_S 23 44 #define DDR_TMRD(x) (((x) & DDR_TMRD_M) << DDR_TMRD_S) 45 #define DDR_CAS_L_M 0x17 46 #define DDR_CAS_L_S 27 47 #define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) 48 #define DDR_OPEN BIT(30) 49 #define DDR1_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ 50 DDR_TRP(6) | DDR_TRRD(4) | \ 51 DDR_TRFC(7) | DDR_TMRD(5) | \ 52 DDR_CAS_L(7) | DDR_OPEN) 53 #define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \ 54 DDR_TRP(9) | DDR_TRRD(7) | \ 55 DDR_TRFC(21) | DDR_TMRD(15) | \ 56 DDR_CAS_L(17) | DDR_OPEN) 57 58 #define DDR_BURST_LEN_S 0 59 #define DDR_BURST_LEN_M 0xf 60 #define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S) 61 #define DDR_BURST_TYPE BIT(4) 62 #define DDR_CNTL_OE_EN BIT(5) 63 #define DDR_PHASE_SEL BIT(6) 64 #define DDR_CKE BIT(7) 65 #define DDR_TWR_S 8 66 #define DDR_TWR_M 0xf 67 #define DDR_TWR(x) (((x) & DDR_TWR_M) << DDR_TWR_S) 68 #define DDR_TRTW_S 12 69 #define DDR_TRTW_M 0x1f 70 #define DDR_TRTW(x) (((x) & DDR_TRTW_M) << DDR_TRTW_S) 71 #define DDR_TRTP_S 17 72 #define DDR_TRTP_M 0xf 73 #define DDR_TRTP(x) (((x) & DDR_TRTP_M) << DDR_TRTP_S) 74 #define DDR_TWTR_S 21 75 #define DDR_TWTR_M 0x1f 76 #define DDR_TWTR(x) (((x) & DDR_TWTR_M) << DDR_TWTR_S) 77 #define DDR_G_OPEN_L_S 26 78 #define DDR_G_OPEN_L_M 0xf 79 #define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S) 80 #define DDR_HALF_WIDTH_LOW BIT(31) 81 #define DDR1_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \ 82 DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \ 83 DDR_TRTP(8) | DDR_TWTR(14) | \ 84 DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW) 85 #define DDR2_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \ 86 DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \ 87 DDR_TRTP(9) | DDR_TWTR(21) | \ 88 DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW) 89 90 #define DDR_TWR_MSB BIT(3) 91 #define DDR_TRAS_MSB BIT(2) 92 #define DDR_TRFC_MSB_M 0x3 93 #define DDR_TRFC_MSB(x) (x) 94 #define DDR1_CONF3_REG_VAL 0 95 #define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2)) 96 97 #define DDR_CTL_SRAM_TSEL BIT(30) 98 #define DDR_CTL_SRAM_GE0_SYNC BIT(20) 99 #define DDR_CTL_SRAM_GE1_SYNC BIT(19) 100 #define DDR_CTL_SRAM_USB_SYNC BIT(18) 101 #define DDR_CTL_SRAM_PCIE_SYNC BIT(17) 102 #define DDR_CTL_SRAM_WMAC_SYNC BIT(16) 103 #define DDR_CTL_SRAM_MISC1_SYNC BIT(15) 104 #define DDR_CTL_SRAM_MISC2_SYNC BIT(14) 105 #define DDR_CTL_PAD_DDR2_SEL BIT(6) 106 #define DDR_CTL_HALF_WIDTH BIT(1) 107 #define DDR_CTL_CONFIG_VAL (DDR_CTL_SRAM_TSEL | \ 108 DDR_CTL_SRAM_GE0_SYNC | \ 109 DDR_CTL_SRAM_GE1_SYNC | \ 110 DDR_CTL_SRAM_USB_SYNC | \ 111 DDR_CTL_SRAM_PCIE_SYNC | \ 112 DDR_CTL_SRAM_WMAC_SYNC | \ 113 DDR_CTL_HALF_WIDTH) 114 115 #define DDR_BURST_GE0_MAX_BL_S 0 116 #define DDR_BURST_GE0_MAX_BL_M 0xf 117 #define DDR_BURST_GE0_MAX_BL(x) \ 118 (((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S) 119 #define DDR_BURST_GE1_MAX_BL_S 4 120 #define DDR_BURST_GE1_MAX_BL_M 0xf 121 #define DDR_BURST_GE1_MAX_BL(x) \ 122 (((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S) 123 #define DDR_BURST_PCIE_MAX_BL_S 8 124 #define DDR_BURST_PCIE_MAX_BL_M 0xf 125 #define DDR_BURST_PCIE_MAX_BL(x) \ 126 (((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S) 127 #define DDR_BURST_USB_MAX_BL_S 12 128 #define DDR_BURST_USB_MAX_BL_M 0xf 129 #define DDR_BURST_USB_MAX_BL(x) \ 130 (((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S) 131 #define DDR_BURST_CPU_MAX_BL_S 16 132 #define DDR_BURST_CPU_MAX_BL_M 0xf 133 #define DDR_BURST_CPU_MAX_BL(x) \ 134 (((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S) 135 #define DDR_BURST_RD_MAX_BL_S 20 136 #define DDR_BURST_RD_MAX_BL_M 0xf 137 #define DDR_BURST_RD_MAX_BL(x) \ 138 (((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S) 139 #define DDR_BURST_WR_MAX_BL_S 24 140 #define DDR_BURST_WR_MAX_BL_M 0xf 141 #define DDR_BURST_WR_MAX_BL(x) \ 142 (((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S) 143 #define DDR_BURST_RWP_MASK_EN_S 28 144 #define DDR_BURST_RWP_MASK_EN_M 0x3 145 #define DDR_BURST_RWP_MASK_EN(x) \ 146 (((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S) 147 #define DDR_BURST_CPU_PRI_BE BIT(30) 148 #define DDR_BURST_CPU_PRI BIT(31) 149 #define DDR_BURST_VAL (DDR_BURST_CPU_PRI_BE | \ 150 DDR_BURST_RWP_MASK_EN(3) | \ 151 DDR_BURST_WR_MAX_BL(4) | \ 152 DDR_BURST_RD_MAX_BL(4) | \ 153 DDR_BURST_CPU_MAX_BL(4) | \ 154 DDR_BURST_USB_MAX_BL(4) | \ 155 DDR_BURST_PCIE_MAX_BL(4) | \ 156 DDR_BURST_GE1_MAX_BL(4) | \ 157 DDR_BURST_GE0_MAX_BL(4)) 158 159 #define DDR_BURST_WMAC_MAX_BL_S 0 160 #define DDR_BURST_WMAC_MAX_BL_M 0xf 161 #define DDR_BURST_WMAC_MAX_BL(x) \ 162 (((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S) 163 #define DDR_BURST2_VAL DDR_BURST_WMAC_MAX_BL(4) 164 165 #define DDR2_CONF_TWL_S 10 166 #define DDR2_CONF_TWL_M 0xf 167 #define DDR2_CONF_TWL(x) \ 168 (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S) 169 #define DDR2_CONF_ODT BIT(9) 170 #define DDR2_CONF_TFAW_S 2 171 #define DDR2_CONF_TFAW_M 0x3f 172 #define DDR2_CONF_TFAW(x) \ 173 (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S) 174 #define DDR2_CONF_EN BIT(0) 175 #define DDR2_CONF_VAL (DDR2_CONF_TWL(5) | \ 176 DDR2_CONF_TFAW(31) | \ 177 DDR2_CONF_ODT | \ 178 DDR2_CONF_EN) 179 180 #define DDR1_EXT_MODE_VAL 0 181 #define DDR2_EXT_MODE_VAL 0x402 182 #define DDR2_EXT_MODE_OCD_VAL 0x782 183 #define DDR1_MODE_DLL_VAL 0x133 184 #define DDR2_MODE_DLL_VAL 0x143 185 #define DDR1_MODE_VAL 0x33 186 #define DDR2_MODE_VAL 0x43 187 #define DDR1_TAP_VAL 0x20 188 #define DDR2_TAP_VAL 0x10 189 190 #define DDR_REG_BIST_MASK_ADDR_0 0x2c 191 #define DDR_REG_BIST_MASK_ADDR_1 0x30 192 #define DDR_REG_BIST_MASK_AHB_GE0_0 0x34 193 #define DDR_REG_BIST_COMP_AHB_GE0_0 0x38 194 #define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c 195 #define DDR_REG_BIST_COMP_AHB_GE1_0 0x40 196 #define DDR_REG_BIST_COMP_ADDR_0 0x64 197 #define DDR_REG_BIST_COMP_ADDR_1 0x68 198 #define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c 199 #define DDR_REG_BIST_COMP_AHB_GE0_1 0x70 200 #define DDR_REG_BIST_MASK_AHB_GE1_1 0x74 201 #define DDR_REG_BIST_COMP_AHB_GE1_1 0x78 202 #define DDR_REG_BIST 0x11c 203 #define DDR_REG_BIST_STATUS 0x120 204 205 #define DDR_BIST_COMP_CNT_S 1 206 #define DDR_BIST_COMP_CNT_M 0xff 207 #define DDR_BIST_COMP_CNT(x) \ 208 (((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S) 209 #define DDR_BIST_COMP_CNT_MASK \ 210 (DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S) 211 #define DDR_BIST_TEST_START BIT(0) 212 #define DDR_BIST_STATUS_DONE BIT(0) 213 214 /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */ 215 #define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f 216 217 #define DDR_TAP_MAGIC_VAL 0xaa55aa55 218 #define DDR_TAP_MAX_VAL 0x40 219 220 void ddr_init(void) 221 { 222 void __iomem *regs; 223 u32 val; 224 225 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, 226 MAP_NOCACHE); 227 val = ath79_get_bootstrap(); 228 if (val & QCA953X_BOOTSTRAP_DDR1) { 229 writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF); 230 udelay(10); 231 232 /* For 16-bit DDR */ 233 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); 234 udelay(100); 235 236 /* Burst size */ 237 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); 238 udelay(100); 239 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); 240 udelay(100); 241 242 /* AHB maximum timeout */ 243 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); 244 udelay(100); 245 246 /* DRAM timing */ 247 writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); 248 udelay(100); 249 writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); 250 udelay(100); 251 writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); 252 udelay(100); 253 254 /* Precharge All */ 255 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); 256 udelay(100); 257 258 /* ODT disable, Full strength, Enable DLL */ 259 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); 260 udelay(100); 261 262 /* Update Extended Mode Register Set (EMRS) */ 263 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); 264 udelay(100); 265 266 /* Reset DLL, CAS Latency 3, Burst Length 8 */ 267 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); 268 udelay(100); 269 270 /* Update Mode Register Set (MRS) */ 271 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); 272 udelay(100); 273 274 /* Precharge All */ 275 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); 276 udelay(100); 277 278 /* Auto Refresh */ 279 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); 280 udelay(100); 281 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); 282 udelay(100); 283 284 /* Normal DLL, CAS Latency 3, Burst Length 8 */ 285 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); 286 udelay(100); 287 288 /* Update Mode Register Set (MRS) */ 289 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); 290 udelay(100); 291 292 /* Refresh time control */ 293 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); 294 udelay(100); 295 296 /* DQS 0 Tap Control */ 297 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); 298 299 /* DQS 1 Tap Control */ 300 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); 301 } else { 302 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); 303 udelay(10); 304 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); 305 udelay(10); 306 writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL, 307 regs + QCA953X_DDR_REG_CTL_CONF); 308 udelay(10); 309 310 /* For 16-bit DDR */ 311 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); 312 udelay(100); 313 314 /* Burst size */ 315 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); 316 udelay(100); 317 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); 318 udelay(100); 319 320 /* AHB maximum timeout */ 321 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); 322 udelay(100); 323 324 /* DRAM timing */ 325 writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); 326 udelay(100); 327 writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); 328 udelay(100); 329 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); 330 udelay(100); 331 332 /* Enable DDR2 */ 333 writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG); 334 udelay(100); 335 336 /* Precharge All */ 337 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); 338 udelay(100); 339 340 /* Update Extended Mode Register 2 Set (EMR2S) */ 341 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); 342 udelay(100); 343 344 /* Update Extended Mode Register 3 Set (EMR3S) */ 345 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); 346 udelay(100); 347 348 /* 150 ohm, Reduced strength, Enable DLL */ 349 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); 350 udelay(100); 351 352 /* Update Extended Mode Register Set (EMRS) */ 353 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); 354 udelay(100); 355 356 /* Reset DLL, CAS Latency 4, Burst Length 8 */ 357 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); 358 udelay(100); 359 360 /* Update Mode Register Set (MRS) */ 361 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); 362 udelay(100); 363 364 /* Precharge All */ 365 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); 366 udelay(100); 367 368 /* Auto Refresh */ 369 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); 370 udelay(100); 371 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); 372 udelay(100); 373 374 /* Normal DLL, CAS Latency 4, Burst Length 8 */ 375 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); 376 udelay(100); 377 378 /* Mode Register Set (MRS) */ 379 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); 380 udelay(100); 381 382 /* Enable OCD, Enable DLL, Reduced Drive Strength */ 383 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR); 384 udelay(100); 385 386 /* Update Extended Mode Register Set (EMRS) */ 387 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); 388 udelay(100); 389 390 /* OCD diable, Enable DLL, Reduced Drive Strength */ 391 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); 392 udelay(100); 393 394 /* Update Extended Mode Register Set (EMRS) */ 395 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); 396 udelay(100); 397 398 /* Refresh time control */ 399 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); 400 udelay(100); 401 402 /* DQS 0 Tap Control */ 403 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); 404 405 /* DQS 1 Tap Control */ 406 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); 407 } 408 } 409 410 void ddr_tap_tuning(void) 411 { 412 void __iomem *regs; 413 u32 val, pass, tap, cnt, tap_val, last, first; 414 415 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, 416 MAP_NOCACHE); 417 418 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); 419 first = DDR_TAP_MAGIC_VAL; 420 last = 0; 421 cnt = 0; 422 tap = 0; 423 424 do { 425 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0); 426 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); 427 428 writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1); 429 writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0); 430 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1); 431 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0); 432 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1); 433 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0); 434 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1); 435 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0); 436 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1); 437 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0); 438 439 /* Start BIST test */ 440 writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST); 441 442 do { 443 val = readl(regs + DDR_REG_BIST_STATUS); 444 } while (!(val & DDR_BIST_STATUS_DONE)); 445 446 /* Stop BIST test */ 447 writel(0, regs + DDR_REG_BIST); 448 449 pass = val & DDR_BIST_COMP_CNT_MASK; 450 pass ^= DDR_BIST_COMP_CNT(8); 451 if (!pass) { 452 if (first != DDR_TAP_MAGIC_VAL) { 453 last = tap; 454 } else { 455 first = tap; 456 last = tap; 457 } 458 cnt++; 459 } 460 tap++; 461 } while (tap < DDR_TAP_MAX_VAL); 462 463 if (cnt) { 464 tap_val = (first + last) / 2; 465 tap_val %= DDR_TAP_MAX_VAL; 466 } 467 468 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0); 469 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); 470 } 471