1 /* 2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <usb.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <phys2bus.h> 15 #include <usbroothubdes.h> 16 #include <wait_bit.h> 17 #include <asm/io.h> 18 #include <power/regulator.h> 19 20 #include "dwc2.h" 21 22 /* Use only HC channel 0. */ 23 #define DWC2_HC_CHANNEL 0 24 25 #define DWC2_STATUS_BUF_SIZE 64 26 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024) 27 28 #define MAX_DEVICE 16 29 #define MAX_ENDPOINT 16 30 31 struct dwc2_priv { 32 #ifdef CONFIG_DM_USB 33 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 34 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); 35 #ifdef CONFIG_DM_REGULATOR 36 struct udevice *vbus_supply; 37 #endif 38 #else 39 uint8_t *aligned_buffer; 40 uint8_t *status_buffer; 41 #endif 42 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 43 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; 44 struct dwc2_core_regs *regs; 45 int root_hub_devnum; 46 bool ext_vbus; 47 /* 48 * The hnp/srp capability must be disabled if the platform 49 * does't support hnp/srp. Otherwise the force mode can't work. 50 */ 51 bool hnp_srp_disable; 52 bool oc_disable; 53 }; 54 55 #ifndef CONFIG_DM_USB 56 /* We need cacheline-aligned buffers for DMA transfers and dcache support */ 57 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 58 ARCH_DMA_MINALIGN); 59 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 60 ARCH_DMA_MINALIGN); 61 62 static struct dwc2_priv local; 63 #endif 64 65 /* 66 * DWC2 IP interface 67 */ 68 69 /* 70 * Initializes the FSLSPClkSel field of the HCFG register 71 * depending on the PHY type. 72 */ 73 static void init_fslspclksel(struct dwc2_core_regs *regs) 74 { 75 uint32_t phyclk; 76 77 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 78 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 79 #else 80 /* High speed PHY running at full speed or high speed */ 81 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; 82 #endif 83 84 #ifdef CONFIG_DWC2_ULPI_FS_LS 85 uint32_t hwcfg2 = readl(®s->ghwcfg2); 86 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 87 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 88 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 89 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 90 91 if (hval == 2 && fval == 1) 92 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ 93 #endif 94 95 clrsetbits_le32(®s->host_regs.hcfg, 96 DWC2_HCFG_FSLSPCLKSEL_MASK, 97 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); 98 } 99 100 /* 101 * Flush a Tx FIFO. 102 * 103 * @param regs Programming view of DWC_otg controller. 104 * @param num Tx FIFO to flush. 105 */ 106 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) 107 { 108 int ret; 109 110 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), 111 ®s->grstctl); 112 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 113 false, 1000, false); 114 if (ret) 115 dev_info(dev, "%s: Timeout!\n", __func__); 116 117 /* Wait for 3 PHY Clocks */ 118 udelay(1); 119 } 120 121 /* 122 * Flush Rx FIFO. 123 * 124 * @param regs Programming view of DWC_otg controller. 125 */ 126 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) 127 { 128 int ret; 129 130 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); 131 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 132 false, 1000, false); 133 if (ret) 134 dev_info(dev, "%s: Timeout!\n", __func__); 135 136 /* Wait for 3 PHY Clocks */ 137 udelay(1); 138 } 139 140 /* 141 * Do core a soft reset of the core. Be careful with this because it 142 * resets all the internal state machines of the core. 143 */ 144 static void dwc_otg_core_reset(struct dwc2_core_regs *regs) 145 { 146 int ret; 147 148 /* Wait for AHB master IDLE state. */ 149 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 150 true, 1000, false); 151 if (ret) 152 dev_info(dev, "%s: Timeout!\n", __func__); 153 154 /* Core Soft Reset */ 155 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); 156 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 157 false, 1000, false); 158 if (ret) 159 dev_info(dev, "%s: Timeout!\n", __func__); 160 161 /* 162 * Wait for core to come out of reset. 163 * NOTE: This long sleep is _very_ important, otherwise the core will 164 * not stay in host mode after a connector ID change! 165 */ 166 mdelay(100); 167 } 168 169 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) 170 static int dwc_vbus_supply_init(struct udevice *dev) 171 { 172 struct dwc2_priv *priv = dev_get_priv(dev); 173 int ret; 174 175 ret = device_get_supply_regulator(dev, "vbus-supply", 176 &priv->vbus_supply); 177 if (ret) { 178 debug("%s: No vbus supply\n", dev->name); 179 return 0; 180 } 181 182 ret = regulator_set_enable(priv->vbus_supply, true); 183 if (ret) { 184 dev_err(dev, "Error enabling vbus supply\n"); 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int dwc_vbus_supply_exit(struct udevice *dev) 192 { 193 struct dwc2_priv *priv = dev_get_priv(dev); 194 int ret; 195 196 if (priv->vbus_supply) { 197 ret = regulator_set_enable(priv->vbus_supply, false); 198 if (ret) { 199 dev_err(dev, "Error disabling vbus supply\n"); 200 return ret; 201 } 202 } 203 204 return 0; 205 } 206 #else 207 static int dwc_vbus_supply_init(struct udevice *dev) 208 { 209 return 0; 210 } 211 212 #if defined(CONFIG_DM_USB) 213 static int dwc_vbus_supply_exit(struct udevice *dev) 214 { 215 return 0; 216 } 217 #endif 218 #endif 219 220 /* 221 * This function initializes the DWC_otg controller registers for 222 * host mode. 223 * 224 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the 225 * request queues. Host channels are reset to ensure that they are ready for 226 * performing transfers. 227 * 228 * @param dev USB Device (NULL if driver model is not being used) 229 * @param regs Programming view of DWC_otg controller 230 * 231 */ 232 static void dwc_otg_core_host_init(struct udevice *dev, 233 struct dwc2_core_regs *regs) 234 { 235 uint32_t nptxfifosize = 0; 236 uint32_t ptxfifosize = 0; 237 uint32_t hprt0 = 0; 238 int i, ret, num_channels; 239 240 /* Restart the Phy Clock */ 241 writel(0, ®s->pcgcctl); 242 243 /* Initialize Host Configuration Register */ 244 init_fslspclksel(regs); 245 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL 246 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); 247 #endif 248 249 /* Configure data FIFO sizes */ 250 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO 251 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { 252 /* Rx FIFO */ 253 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); 254 255 /* Non-periodic Tx FIFO */ 256 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << 257 DWC2_FIFOSIZE_DEPTH_OFFSET; 258 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << 259 DWC2_FIFOSIZE_STARTADDR_OFFSET; 260 writel(nptxfifosize, ®s->gnptxfsiz); 261 262 /* Periodic Tx FIFO */ 263 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << 264 DWC2_FIFOSIZE_DEPTH_OFFSET; 265 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + 266 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << 267 DWC2_FIFOSIZE_STARTADDR_OFFSET; 268 writel(ptxfifosize, ®s->hptxfsiz); 269 } 270 #endif 271 272 /* Clear Host Set HNP Enable in the OTG Control Register */ 273 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); 274 275 /* Make sure the FIFOs are flushed. */ 276 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ 277 dwc_otg_flush_rx_fifo(regs); 278 279 /* Flush out any leftover queued requests. */ 280 num_channels = readl(®s->ghwcfg2); 281 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; 282 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; 283 num_channels += 1; 284 285 for (i = 0; i < num_channels; i++) 286 clrsetbits_le32(®s->hc_regs[i].hcchar, 287 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, 288 DWC2_HCCHAR_CHDIS); 289 290 /* Halt all channels to put them into a known state. */ 291 for (i = 0; i < num_channels; i++) { 292 clrsetbits_le32(®s->hc_regs[i].hcchar, 293 DWC2_HCCHAR_EPDIR, 294 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); 295 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar, 296 DWC2_HCCHAR_CHEN, false, 1000, false); 297 if (ret) 298 dev_info("%s: Timeout!\n", __func__); 299 } 300 301 /* Turn on the vbus power. */ 302 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { 303 hprt0 = readl(®s->hprt0); 304 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); 305 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); 306 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { 307 hprt0 |= DWC2_HPRT0_PRTPWR; 308 writel(hprt0, ®s->hprt0); 309 } 310 } 311 312 if (dev) 313 dwc_vbus_supply_init(dev); 314 } 315 316 /* 317 * This function initializes the DWC_otg controller registers and 318 * prepares the core for device mode or host mode operation. 319 * 320 * @param regs Programming view of the DWC_otg controller 321 */ 322 static void dwc_otg_core_init(struct dwc2_priv *priv) 323 { 324 struct dwc2_core_regs *regs = priv->regs; 325 uint32_t ahbcfg = 0; 326 uint32_t usbcfg = 0; 327 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; 328 329 /* Common Initialization */ 330 usbcfg = readl(®s->gusbcfg); 331 332 /* Program the ULPI External VBUS bit if needed */ 333 if (priv->ext_vbus) { 334 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 335 if (!priv->oc_disable) { 336 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | 337 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH; 338 } 339 } else { 340 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; 341 } 342 343 /* Set external TS Dline pulsing */ 344 #ifdef CONFIG_DWC2_TS_DLINE 345 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 346 #else 347 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; 348 #endif 349 writel(usbcfg, ®s->gusbcfg); 350 351 /* Reset the Controller */ 352 dwc_otg_core_reset(regs); 353 354 /* 355 * This programming sequence needs to happen in FS mode before 356 * any other programming occurs 357 */ 358 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ 359 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) 360 /* If FS mode with FS PHY */ 361 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); 362 363 /* Reset after a PHY select */ 364 dwc_otg_core_reset(regs); 365 366 /* 367 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. 368 * Also do this on HNP Dev/Host mode switches (done in dev_init 369 * and host_init). 370 */ 371 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 372 init_fslspclksel(regs); 373 374 #ifdef CONFIG_DWC2_I2C_ENABLE 375 /* Program GUSBCFG.OtgUtmifsSel to I2C */ 376 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); 377 378 /* Program GI2CCTL.I2CEn */ 379 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | 380 DWC2_GI2CCTL_I2CDEVADDR_MASK, 381 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); 382 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); 383 #endif 384 385 #else 386 /* High speed PHY. */ 387 388 /* 389 * HS PHY parameters. These parameters are preserved during 390 * soft reset so only program the first time. Do a soft reset 391 * immediately after setting phyif. 392 */ 393 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); 394 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; 395 396 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ 397 #ifdef CONFIG_DWC2_PHY_ULPI_DDR 398 usbcfg |= DWC2_GUSBCFG_DDRSEL; 399 #else 400 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; 401 #endif 402 } else { /* UTMI+ interface */ 403 #if (CONFIG_DWC2_UTMI_WIDTH == 16) 404 usbcfg |= DWC2_GUSBCFG_PHYIF; 405 #endif 406 } 407 408 writel(usbcfg, ®s->gusbcfg); 409 410 /* Reset after setting the PHY parameters */ 411 dwc_otg_core_reset(regs); 412 #endif 413 414 usbcfg = readl(®s->gusbcfg); 415 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); 416 #ifdef CONFIG_DWC2_ULPI_FS_LS 417 uint32_t hwcfg2 = readl(®s->ghwcfg2); 418 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> 419 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; 420 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> 421 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; 422 if (hval == 2 && fval == 1) { 423 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; 424 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; 425 } 426 #endif 427 if (priv->hnp_srp_disable) 428 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; 429 430 writel(usbcfg, ®s->gusbcfg); 431 432 /* Program the GAHBCFG Register. */ 433 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { 434 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: 435 break; 436 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: 437 while (brst_sz > 1) { 438 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); 439 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; 440 brst_sz >>= 1; 441 } 442 443 #ifdef CONFIG_DWC2_DMA_ENABLE 444 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 445 #endif 446 break; 447 448 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: 449 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; 450 #ifdef CONFIG_DWC2_DMA_ENABLE 451 ahbcfg |= DWC2_GAHBCFG_DMAENABLE; 452 #endif 453 break; 454 } 455 456 writel(ahbcfg, ®s->gahbcfg); 457 458 /* Program the capabilities in GUSBCFG Register */ 459 usbcfg = 0; 460 461 if (!priv->hnp_srp_disable) 462 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; 463 #ifdef CONFIG_DWC2_IC_USB_CAP 464 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; 465 #endif 466 467 setbits_le32(®s->gusbcfg, usbcfg); 468 } 469 470 /* 471 * Prepares a host channel for transferring packets to/from a specific 472 * endpoint. The HCCHARn register is set up with the characteristics specified 473 * in _hc. Host channel interrupts that may need to be serviced while this 474 * transfer is in progress are enabled. 475 * 476 * @param regs Programming view of DWC_otg controller 477 * @param hc Information needed to initialize the host channel 478 */ 479 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, 480 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, 481 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) 482 { 483 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; 484 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | 485 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | 486 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | 487 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | 488 (max_packet << DWC2_HCCHAR_MPS_OFFSET); 489 490 if (dev->speed == USB_SPEED_LOW) 491 hcchar |= DWC2_HCCHAR_LSPDDEV; 492 493 /* 494 * Program the HCCHARn register with the endpoint characteristics 495 * for the current transfer. 496 */ 497 writel(hcchar, &hc_regs->hcchar); 498 499 /* Program the HCSPLIT register, default to no SPLIT */ 500 writel(0, &hc_regs->hcsplt); 501 } 502 503 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, 504 uint8_t hub_devnum, uint8_t hub_port) 505 { 506 uint32_t hcsplt = 0; 507 508 hcsplt = DWC2_HCSPLT_SPLTENA; 509 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; 510 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; 511 512 /* Program the HCSPLIT register for SPLITs */ 513 writel(hcsplt, &hc_regs->hcsplt); 514 } 515 516 /* 517 * DWC2 to USB API interface 518 */ 519 /* Direction: In ; Request: Status */ 520 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, 521 struct usb_device *dev, void *buffer, 522 int txlen, struct devrequest *cmd) 523 { 524 uint32_t hprt0 = 0; 525 uint32_t port_status = 0; 526 uint32_t port_change = 0; 527 int len = 0; 528 int stat = 0; 529 530 switch (cmd->requesttype & ~USB_DIR_IN) { 531 case 0: 532 *(uint16_t *)buffer = cpu_to_le16(1); 533 len = 2; 534 break; 535 case USB_RECIP_INTERFACE: 536 case USB_RECIP_ENDPOINT: 537 *(uint16_t *)buffer = cpu_to_le16(0); 538 len = 2; 539 break; 540 case USB_TYPE_CLASS: 541 *(uint32_t *)buffer = cpu_to_le32(0); 542 len = 4; 543 break; 544 case USB_RECIP_OTHER | USB_TYPE_CLASS: 545 hprt0 = readl(®s->hprt0); 546 if (hprt0 & DWC2_HPRT0_PRTCONNSTS) 547 port_status |= USB_PORT_STAT_CONNECTION; 548 if (hprt0 & DWC2_HPRT0_PRTENA) 549 port_status |= USB_PORT_STAT_ENABLE; 550 if (hprt0 & DWC2_HPRT0_PRTSUSP) 551 port_status |= USB_PORT_STAT_SUSPEND; 552 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) 553 port_status |= USB_PORT_STAT_OVERCURRENT; 554 if (hprt0 & DWC2_HPRT0_PRTRST) 555 port_status |= USB_PORT_STAT_RESET; 556 if (hprt0 & DWC2_HPRT0_PRTPWR) 557 port_status |= USB_PORT_STAT_POWER; 558 559 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) 560 port_status |= USB_PORT_STAT_LOW_SPEED; 561 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 562 DWC2_HPRT0_PRTSPD_HIGH) 563 port_status |= USB_PORT_STAT_HIGH_SPEED; 564 565 if (hprt0 & DWC2_HPRT0_PRTENCHNG) 566 port_change |= USB_PORT_STAT_C_ENABLE; 567 if (hprt0 & DWC2_HPRT0_PRTCONNDET) 568 port_change |= USB_PORT_STAT_C_CONNECTION; 569 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) 570 port_change |= USB_PORT_STAT_C_OVERCURRENT; 571 572 *(uint32_t *)buffer = cpu_to_le32(port_status | 573 (port_change << 16)); 574 len = 4; 575 break; 576 default: 577 puts("unsupported root hub command\n"); 578 stat = USB_ST_STALLED; 579 } 580 581 dev->act_len = min(len, txlen); 582 dev->status = stat; 583 584 return stat; 585 } 586 587 /* Direction: In ; Request: Descriptor */ 588 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, 589 void *buffer, int txlen, 590 struct devrequest *cmd) 591 { 592 unsigned char data[32]; 593 uint32_t dsc; 594 int len = 0; 595 int stat = 0; 596 uint16_t wValue = cpu_to_le16(cmd->value); 597 uint16_t wLength = cpu_to_le16(cmd->length); 598 599 switch (cmd->requesttype & ~USB_DIR_IN) { 600 case 0: 601 switch (wValue & 0xff00) { 602 case 0x0100: /* device descriptor */ 603 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); 604 memcpy(buffer, root_hub_dev_des, len); 605 break; 606 case 0x0200: /* configuration descriptor */ 607 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); 608 memcpy(buffer, root_hub_config_des, len); 609 break; 610 case 0x0300: /* string descriptors */ 611 switch (wValue & 0xff) { 612 case 0x00: 613 len = min3(txlen, (int)sizeof(root_hub_str_index0), 614 (int)wLength); 615 memcpy(buffer, root_hub_str_index0, len); 616 break; 617 case 0x01: 618 len = min3(txlen, (int)sizeof(root_hub_str_index1), 619 (int)wLength); 620 memcpy(buffer, root_hub_str_index1, len); 621 break; 622 } 623 break; 624 default: 625 stat = USB_ST_STALLED; 626 } 627 break; 628 629 case USB_TYPE_CLASS: 630 /* Root port config, set 1 port and nothing else. */ 631 dsc = 0x00000001; 632 633 data[0] = 9; /* min length; */ 634 data[1] = 0x29; 635 data[2] = dsc & RH_A_NDP; 636 data[3] = 0; 637 if (dsc & RH_A_PSM) 638 data[3] |= 0x1; 639 if (dsc & RH_A_NOCP) 640 data[3] |= 0x10; 641 else if (dsc & RH_A_OCPM) 642 data[3] |= 0x8; 643 644 /* corresponds to data[4-7] */ 645 data[5] = (dsc & RH_A_POTPGT) >> 24; 646 data[7] = dsc & RH_B_DR; 647 if (data[2] < 7) { 648 data[8] = 0xff; 649 } else { 650 data[0] += 2; 651 data[8] = (dsc & RH_B_DR) >> 8; 652 data[9] = 0xff; 653 data[10] = data[9]; 654 } 655 656 len = min3(txlen, (int)data[0], (int)wLength); 657 memcpy(buffer, data, len); 658 break; 659 default: 660 puts("unsupported root hub command\n"); 661 stat = USB_ST_STALLED; 662 } 663 664 dev->act_len = min(len, txlen); 665 dev->status = stat; 666 667 return stat; 668 } 669 670 /* Direction: In ; Request: Configuration */ 671 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, 672 void *buffer, int txlen, 673 struct devrequest *cmd) 674 { 675 int len = 0; 676 int stat = 0; 677 678 switch (cmd->requesttype & ~USB_DIR_IN) { 679 case 0: 680 *(uint8_t *)buffer = 0x01; 681 len = 1; 682 break; 683 default: 684 puts("unsupported root hub command\n"); 685 stat = USB_ST_STALLED; 686 } 687 688 dev->act_len = min(len, txlen); 689 dev->status = stat; 690 691 return stat; 692 } 693 694 /* Direction: In */ 695 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, 696 struct usb_device *dev, void *buffer, 697 int txlen, struct devrequest *cmd) 698 { 699 switch (cmd->request) { 700 case USB_REQ_GET_STATUS: 701 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, 702 txlen, cmd); 703 case USB_REQ_GET_DESCRIPTOR: 704 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, 705 txlen, cmd); 706 case USB_REQ_GET_CONFIGURATION: 707 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, 708 txlen, cmd); 709 default: 710 puts("unsupported root hub command\n"); 711 return USB_ST_STALLED; 712 } 713 } 714 715 /* Direction: Out */ 716 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, 717 struct usb_device *dev, 718 void *buffer, int txlen, 719 struct devrequest *cmd) 720 { 721 struct dwc2_core_regs *regs = priv->regs; 722 int len = 0; 723 int stat = 0; 724 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); 725 uint16_t wValue = cpu_to_le16(cmd->value); 726 727 switch (bmrtype_breq & ~USB_DIR_IN) { 728 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: 729 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: 730 break; 731 732 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 733 switch (wValue) { 734 case USB_PORT_FEAT_C_CONNECTION: 735 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); 736 break; 737 } 738 break; 739 740 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: 741 switch (wValue) { 742 case USB_PORT_FEAT_SUSPEND: 743 break; 744 745 case USB_PORT_FEAT_RESET: 746 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 747 DWC2_HPRT0_PRTCONNDET | 748 DWC2_HPRT0_PRTENCHNG | 749 DWC2_HPRT0_PRTOVRCURRCHNG, 750 DWC2_HPRT0_PRTRST); 751 mdelay(50); 752 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); 753 break; 754 755 case USB_PORT_FEAT_POWER: 756 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 757 DWC2_HPRT0_PRTCONNDET | 758 DWC2_HPRT0_PRTENCHNG | 759 DWC2_HPRT0_PRTOVRCURRCHNG, 760 DWC2_HPRT0_PRTRST); 761 break; 762 763 case USB_PORT_FEAT_ENABLE: 764 break; 765 } 766 break; 767 case (USB_REQ_SET_ADDRESS << 8): 768 priv->root_hub_devnum = wValue; 769 break; 770 case (USB_REQ_SET_CONFIGURATION << 8): 771 break; 772 default: 773 puts("unsupported root hub command\n"); 774 stat = USB_ST_STALLED; 775 } 776 777 len = min(len, txlen); 778 779 dev->act_len = len; 780 dev->status = stat; 781 782 return stat; 783 } 784 785 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, 786 unsigned long pipe, void *buffer, int txlen, 787 struct devrequest *cmd) 788 { 789 int stat = 0; 790 791 if (usb_pipeint(pipe)) { 792 puts("Root-Hub submit IRQ: NOT implemented\n"); 793 return 0; 794 } 795 796 if (cmd->requesttype & USB_DIR_IN) 797 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); 798 else 799 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); 800 801 mdelay(1); 802 803 return stat; 804 } 805 806 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) 807 { 808 int ret; 809 uint32_t hcint, hctsiz; 810 811 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true, 812 2000, false); 813 if (ret) 814 return ret; 815 816 hcint = readl(&hc_regs->hcint); 817 hctsiz = readl(&hc_regs->hctsiz); 818 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> 819 DWC2_HCTSIZ_XFERSIZE_OFFSET; 820 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; 821 822 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, 823 *toggle); 824 825 if (hcint & DWC2_HCINT_XFERCOMP) 826 return 0; 827 828 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) 829 return -EAGAIN; 830 831 debug("%s: Error (HCINT=%08x)\n", __func__, hcint); 832 return -EINVAL; 833 } 834 835 static int dwc2_eptype[] = { 836 DWC2_HCCHAR_EPTYPE_ISOC, 837 DWC2_HCCHAR_EPTYPE_INTR, 838 DWC2_HCCHAR_EPTYPE_CONTROL, 839 DWC2_HCCHAR_EPTYPE_BULK, 840 }; 841 842 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, 843 u8 *pid, int in, void *buffer, int num_packets, 844 int xfer_len, int *actual_len, int odd_frame) 845 { 846 int ret = 0; 847 uint32_t sub; 848 849 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, 850 *pid, xfer_len, num_packets); 851 852 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | 853 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | 854 (*pid << DWC2_HCTSIZ_PID_OFFSET), 855 &hc_regs->hctsiz); 856 857 if (xfer_len) { 858 if (in) { 859 invalidate_dcache_range( 860 (uintptr_t)aligned_buffer, 861 (uintptr_t)aligned_buffer + 862 roundup(xfer_len, ARCH_DMA_MINALIGN)); 863 } else { 864 memcpy(aligned_buffer, buffer, xfer_len); 865 flush_dcache_range( 866 (uintptr_t)aligned_buffer, 867 (uintptr_t)aligned_buffer + 868 roundup(xfer_len, ARCH_DMA_MINALIGN)); 869 } 870 } 871 872 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); 873 874 /* Clear old interrupt conditions for this host channel. */ 875 writel(0x3fff, &hc_regs->hcint); 876 877 /* Set host channel enable after all other setup is complete. */ 878 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | 879 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | 880 DWC2_HCCHAR_ODDFRM, 881 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | 882 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | 883 DWC2_HCCHAR_CHEN); 884 885 ret = wait_for_chhltd(hc_regs, &sub, pid); 886 if (ret < 0) 887 return ret; 888 889 if (in) { 890 xfer_len -= sub; 891 892 invalidate_dcache_range((unsigned long)aligned_buffer, 893 (unsigned long)aligned_buffer + 894 roundup(xfer_len, ARCH_DMA_MINALIGN)); 895 896 memcpy(buffer, aligned_buffer, xfer_len); 897 } 898 *actual_len = xfer_len; 899 900 return ret; 901 } 902 903 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, 904 unsigned long pipe, u8 *pid, int in, void *buffer, int len) 905 { 906 struct dwc2_core_regs *regs = priv->regs; 907 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; 908 struct dwc2_host_regs *host_regs = ®s->host_regs; 909 int devnum = usb_pipedevice(pipe); 910 int ep = usb_pipeendpoint(pipe); 911 int max = usb_maxpacket(dev, pipe); 912 int eptype = dwc2_eptype[usb_pipetype(pipe)]; 913 int done = 0; 914 int ret = 0; 915 int do_split = 0; 916 int complete_split = 0; 917 uint32_t xfer_len; 918 uint32_t num_packets; 919 int stop_transfer = 0; 920 uint32_t max_xfer_len; 921 int ssplit_frame_num = 0; 922 923 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, 924 in, len); 925 926 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; 927 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) 928 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; 929 if (max_xfer_len > DWC2_DATA_BUF_SIZE) 930 max_xfer_len = DWC2_DATA_BUF_SIZE; 931 932 /* Make sure that max_xfer_len is a multiple of max packet size. */ 933 num_packets = max_xfer_len / max; 934 max_xfer_len = num_packets * max; 935 936 /* Initialize channel */ 937 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, 938 eptype, max); 939 940 /* Check if the target is a FS/LS device behind a HS hub */ 941 if (dev->speed != USB_SPEED_HIGH) { 942 uint8_t hub_addr; 943 uint8_t hub_port; 944 uint32_t hprt0 = readl(®s->hprt0); 945 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == 946 DWC2_HPRT0_PRTSPD_HIGH) { 947 usb_find_usb2_hub_address_port(dev, &hub_addr, 948 &hub_port); 949 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); 950 951 do_split = 1; 952 num_packets = 1; 953 max_xfer_len = max; 954 } 955 } 956 957 do { 958 int actual_len = 0; 959 uint32_t hcint; 960 int odd_frame = 0; 961 xfer_len = len - done; 962 963 if (xfer_len > max_xfer_len) 964 xfer_len = max_xfer_len; 965 else if (xfer_len > max) 966 num_packets = (xfer_len + max - 1) / max; 967 else 968 num_packets = 1; 969 970 if (complete_split) 971 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 972 else if (do_split) 973 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); 974 975 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { 976 int uframe_num = readl(&host_regs->hfnum); 977 if (!(uframe_num & 0x1)) 978 odd_frame = 1; 979 } 980 981 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, 982 in, (char *)buffer + done, num_packets, 983 xfer_len, &actual_len, odd_frame); 984 985 hcint = readl(&hc_regs->hcint); 986 if (complete_split) { 987 stop_transfer = 0; 988 if (hcint & DWC2_HCINT_NYET) { 989 ret = 0; 990 int frame_num = DWC2_HFNUM_MAX_FRNUM & 991 readl(&host_regs->hfnum); 992 if (((frame_num - ssplit_frame_num) & 993 DWC2_HFNUM_MAX_FRNUM) > 4) 994 ret = -EAGAIN; 995 } else 996 complete_split = 0; 997 } else if (do_split) { 998 if (hcint & DWC2_HCINT_ACK) { 999 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & 1000 readl(&host_regs->hfnum); 1001 ret = 0; 1002 complete_split = 1; 1003 } 1004 } 1005 1006 if (ret) 1007 break; 1008 1009 if (actual_len < xfer_len) 1010 stop_transfer = 1; 1011 1012 done += actual_len; 1013 1014 /* Transactions are done when when either all data is transferred or 1015 * there is a short transfer. In case of a SPLIT make sure the CSPLIT 1016 * is executed. 1017 */ 1018 } while (((done < len) && !stop_transfer) || complete_split); 1019 1020 writel(0, &hc_regs->hcintmsk); 1021 writel(0xFFFFFFFF, &hc_regs->hcint); 1022 1023 dev->status = 0; 1024 dev->act_len = done; 1025 1026 return ret; 1027 } 1028 1029 /* U-Boot USB transmission interface */ 1030 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, 1031 unsigned long pipe, void *buffer, int len) 1032 { 1033 int devnum = usb_pipedevice(pipe); 1034 int ep = usb_pipeendpoint(pipe); 1035 u8* pid; 1036 1037 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { 1038 dev->status = 0; 1039 return -EINVAL; 1040 } 1041 1042 if (usb_pipein(pipe)) 1043 pid = &priv->in_data_toggle[devnum][ep]; 1044 else 1045 pid = &priv->out_data_toggle[devnum][ep]; 1046 1047 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); 1048 } 1049 1050 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, 1051 unsigned long pipe, void *buffer, int len, 1052 struct devrequest *setup) 1053 { 1054 int devnum = usb_pipedevice(pipe); 1055 int ret, act_len; 1056 u8 pid; 1057 /* For CONTROL endpoint pid should start with DATA1 */ 1058 int status_direction; 1059 1060 if (devnum == priv->root_hub_devnum) { 1061 dev->status = 0; 1062 dev->speed = USB_SPEED_HIGH; 1063 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, 1064 setup); 1065 } 1066 1067 /* SETUP stage */ 1068 pid = DWC2_HC_PID_SETUP; 1069 do { 1070 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); 1071 } while (ret == -EAGAIN); 1072 if (ret) 1073 return ret; 1074 1075 /* DATA stage */ 1076 act_len = 0; 1077 if (buffer) { 1078 pid = DWC2_HC_PID_DATA1; 1079 do { 1080 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), 1081 buffer, len); 1082 act_len += dev->act_len; 1083 buffer += dev->act_len; 1084 len -= dev->act_len; 1085 } while (ret == -EAGAIN); 1086 if (ret) 1087 return ret; 1088 status_direction = usb_pipeout(pipe); 1089 } else { 1090 /* No-data CONTROL always ends with an IN transaction */ 1091 status_direction = 1; 1092 } 1093 1094 /* STATUS stage */ 1095 pid = DWC2_HC_PID_DATA1; 1096 do { 1097 ret = chunk_msg(priv, dev, pipe, &pid, status_direction, 1098 priv->status_buffer, 0); 1099 } while (ret == -EAGAIN); 1100 if (ret) 1101 return ret; 1102 1103 dev->act_len = act_len; 1104 1105 return 0; 1106 } 1107 1108 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, 1109 unsigned long pipe, void *buffer, int len, int interval) 1110 { 1111 unsigned long timeout; 1112 int ret; 1113 1114 /* FIXME: what is interval? */ 1115 1116 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); 1117 for (;;) { 1118 if (get_timer(0) > timeout) { 1119 dev_err(dev, "Timeout poll on interrupt endpoint\n"); 1120 return -ETIMEDOUT; 1121 } 1122 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); 1123 if (ret != -EAGAIN) 1124 return ret; 1125 } 1126 } 1127 1128 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) 1129 { 1130 struct dwc2_core_regs *regs = priv->regs; 1131 uint32_t snpsid; 1132 int i, j; 1133 1134 snpsid = readl(®s->gsnpsid); 1135 dev_info(dev, "Core Release: %x.%03x\n", 1136 snpsid >> 12 & 0xf, snpsid & 0xfff); 1137 1138 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && 1139 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { 1140 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n", 1141 snpsid); 1142 return -ENODEV; 1143 } 1144 1145 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS 1146 priv->ext_vbus = 1; 1147 #else 1148 priv->ext_vbus = 0; 1149 #endif 1150 1151 dwc_otg_core_init(priv); 1152 dwc_otg_core_host_init(dev, regs); 1153 1154 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1155 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1156 DWC2_HPRT0_PRTOVRCURRCHNG, 1157 DWC2_HPRT0_PRTRST); 1158 mdelay(50); 1159 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | 1160 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | 1161 DWC2_HPRT0_PRTRST); 1162 1163 for (i = 0; i < MAX_DEVICE; i++) { 1164 for (j = 0; j < MAX_ENDPOINT; j++) { 1165 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1166 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; 1167 } 1168 } 1169 1170 /* 1171 * Add a 1 second delay here. This gives the host controller 1172 * a bit time before the comminucation with the USB devices 1173 * is started (the bus is scanned) and fixes the USB detection 1174 * problems with some problematic USB keys. 1175 */ 1176 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) 1177 mdelay(1000); 1178 1179 return 0; 1180 } 1181 1182 static void dwc2_uninit_common(struct dwc2_core_regs *regs) 1183 { 1184 /* Put everything in reset. */ 1185 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | 1186 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | 1187 DWC2_HPRT0_PRTOVRCURRCHNG, 1188 DWC2_HPRT0_PRTRST); 1189 } 1190 1191 #ifndef CONFIG_DM_USB 1192 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1193 int len, struct devrequest *setup) 1194 { 1195 return _submit_control_msg(&local, dev, pipe, buffer, len, setup); 1196 } 1197 1198 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1199 int len) 1200 { 1201 return _submit_bulk_msg(&local, dev, pipe, buffer, len); 1202 } 1203 1204 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1205 int len, int interval) 1206 { 1207 return _submit_int_msg(&local, dev, pipe, buffer, len, interval); 1208 } 1209 1210 /* U-Boot USB control interface */ 1211 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1212 { 1213 struct dwc2_priv *priv = &local; 1214 1215 memset(priv, '\0', sizeof(*priv)); 1216 priv->root_hub_devnum = 0; 1217 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; 1218 priv->aligned_buffer = aligned_buffer_addr; 1219 priv->status_buffer = status_buffer_addr; 1220 1221 /* board-dependant init */ 1222 if (board_usb_init(index, USB_INIT_HOST)) 1223 return -1; 1224 1225 return dwc2_init_common(NULL, priv); 1226 } 1227 1228 int usb_lowlevel_stop(int index) 1229 { 1230 dwc2_uninit_common(local.regs); 1231 1232 return 0; 1233 } 1234 #endif 1235 1236 #ifdef CONFIG_DM_USB 1237 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1238 unsigned long pipe, void *buffer, int length, 1239 struct devrequest *setup) 1240 { 1241 struct dwc2_priv *priv = dev_get_priv(dev); 1242 1243 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1244 dev->name, udev, udev->dev->name, udev->portnr); 1245 1246 return _submit_control_msg(priv, udev, pipe, buffer, length, setup); 1247 } 1248 1249 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1250 unsigned long pipe, void *buffer, int length) 1251 { 1252 struct dwc2_priv *priv = dev_get_priv(dev); 1253 1254 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1255 1256 return _submit_bulk_msg(priv, udev, pipe, buffer, length); 1257 } 1258 1259 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1260 unsigned long pipe, void *buffer, int length, 1261 int interval) 1262 { 1263 struct dwc2_priv *priv = dev_get_priv(dev); 1264 1265 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1266 1267 return _submit_int_msg(priv, udev, pipe, buffer, length, interval); 1268 } 1269 1270 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) 1271 { 1272 struct dwc2_priv *priv = dev_get_priv(dev); 1273 fdt_addr_t addr; 1274 1275 addr = dev_read_addr(dev); 1276 if (addr == FDT_ADDR_T_NONE) 1277 return -EINVAL; 1278 priv->regs = (struct dwc2_core_regs *)addr; 1279 1280 priv->oc_disable = dev_read_bool(dev, "disable-over-current"); 1281 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); 1282 1283 return 0; 1284 } 1285 1286 static int dwc2_usb_probe(struct udevice *dev) 1287 { 1288 struct dwc2_priv *priv = dev_get_priv(dev); 1289 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); 1290 1291 bus_priv->desc_before_addr = true; 1292 1293 return dwc2_init_common(dev, priv); 1294 } 1295 1296 static int dwc2_usb_remove(struct udevice *dev) 1297 { 1298 struct dwc2_priv *priv = dev_get_priv(dev); 1299 int ret; 1300 1301 ret = dwc_vbus_supply_exit(dev); 1302 if (ret) 1303 return ret; 1304 1305 dwc2_uninit_common(priv->regs); 1306 1307 return 0; 1308 } 1309 1310 struct dm_usb_ops dwc2_usb_ops = { 1311 .control = dwc2_submit_control_msg, 1312 .bulk = dwc2_submit_bulk_msg, 1313 .interrupt = dwc2_submit_int_msg, 1314 }; 1315 1316 static const struct udevice_id dwc2_usb_ids[] = { 1317 { .compatible = "brcm,bcm2835-usb" }, 1318 { .compatible = "snps,dwc2" }, 1319 { } 1320 }; 1321 1322 U_BOOT_DRIVER(usb_dwc2) = { 1323 .name = "dwc2_usb", 1324 .id = UCLASS_USB, 1325 .of_match = dwc2_usb_ids, 1326 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, 1327 .probe = dwc2_usb_probe, 1328 .remove = dwc2_usb_remove, 1329 .ops = &dwc2_usb_ops, 1330 .priv_auto_alloc_size = sizeof(struct dwc2_priv), 1331 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1332 }; 1333 #endif 1334