1 /* 2 * NVIDIA Tegra SPI controller (T114 and later) 3 * 4 * Copyright (c) 2010-2013 NVIDIA Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch-tegra/clk_rst.h> 14 #include <spi.h> 15 #include "tegra_spi.h" 16 17 /* COMMAND1 */ 18 #define SPI_CMD1_GO BIT(31) 19 #define SPI_CMD1_M_S BIT(30) 20 #define SPI_CMD1_MODE_MASK GENMASK(1, 0) 21 #define SPI_CMD1_MODE_SHIFT 28 22 #define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0) 23 #define SPI_CMD1_CS_SEL_SHIFT 26 24 #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) 25 #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) 26 #define SPI_CMD1_CS_POL_INACTIVE1 BIT(23) 27 #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) 28 #define SPI_CMD1_CS_SW_HW BIT(21) 29 #define SPI_CMD1_CS_SW_VAL BIT(20) 30 #define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0) 31 #define SPI_CMD1_IDLE_SDA_SHIFT 18 32 #define SPI_CMD1_BIDIR BIT(17) 33 #define SPI_CMD1_LSBI_FE BIT(16) 34 #define SPI_CMD1_LSBY_FE BIT(15) 35 #define SPI_CMD1_BOTH_EN_BIT BIT(14) 36 #define SPI_CMD1_BOTH_EN_BYTE BIT(13) 37 #define SPI_CMD1_RX_EN BIT(12) 38 #define SPI_CMD1_TX_EN BIT(11) 39 #define SPI_CMD1_PACKED BIT(5) 40 #define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0) 41 #define SPI_CMD1_BIT_LEN_SHIFT 0 42 43 /* COMMAND2 */ 44 #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) 45 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6) 46 #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) 47 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0) 48 49 /* TRANSFER STATUS */ 50 #define SPI_XFER_STS_RDY BIT(30) 51 52 /* FIFO STATUS */ 53 #define SPI_FIFO_STS_CS_INACTIVE BIT(31) 54 #define SPI_FIFO_STS_FRAME_END BIT(30) 55 #define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) 56 #define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) 57 #define SPI_FIFO_STS_ERR BIT(8) 58 #define SPI_FIFO_STS_TX_FIFO_OVF BIT(7) 59 #define SPI_FIFO_STS_TX_FIFO_UNR BIT(6) 60 #define SPI_FIFO_STS_RX_FIFO_OVF BIT(5) 61 #define SPI_FIFO_STS_RX_FIFO_UNR BIT(4) 62 #define SPI_FIFO_STS_TX_FIFO_FULL BIT(3) 63 #define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) 64 #define SPI_FIFO_STS_RX_FIFO_FULL BIT(1) 65 #define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) 66 67 #define SPI_TIMEOUT 1000 68 #define TEGRA_SPI_MAX_FREQ 52000000 69 70 struct spi_regs { 71 u32 command1; /* 000:SPI_COMMAND1 register */ 72 u32 command2; /* 004:SPI_COMMAND2 register */ 73 u32 timing1; /* 008:SPI_CS_TIM1 register */ 74 u32 timing2; /* 00c:SPI_CS_TIM2 register */ 75 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ 76 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ 77 u32 tx_data; /* 018:SPI_TX_DATA register */ 78 u32 rx_data; /* 01c:SPI_RX_DATA register */ 79 u32 dma_ctl; /* 020:SPI_DMA_CTL register */ 80 u32 dma_blk; /* 024:SPI_DMA_BLK register */ 81 u32 rsvd[56]; /* 028-107 reserved */ 82 u32 tx_fifo; /* 108:SPI_FIFO1 register */ 83 u32 rsvd2[31]; /* 10c-187 reserved */ 84 u32 rx_fifo; /* 188:SPI_FIFO2 register */ 85 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ 86 }; 87 88 struct tegra114_spi_priv { 89 struct spi_regs *regs; 90 unsigned int freq; 91 unsigned int mode; 92 int periph_id; 93 int valid; 94 int last_transaction_us; 95 }; 96 97 static int tegra114_spi_ofdata_to_platdata(struct udevice *bus) 98 { 99 struct tegra_spi_platdata *plat = bus->platdata; 100 101 plat->base = dev_read_addr(bus); 102 plat->periph_id = clock_decode_periph_id(bus); 103 104 if (plat->periph_id == PERIPH_ID_NONE) { 105 debug("%s: could not decode periph id %d\n", __func__, 106 plat->periph_id); 107 return -FDT_ERR_NOTFOUND; 108 } 109 110 /* Use 500KHz as a suitable default */ 111 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 112 500000); 113 plat->deactivate_delay_us = dev_read_u32_default(bus, 114 "spi-deactivate-delay", 0); 115 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 116 __func__, plat->base, plat->periph_id, plat->frequency, 117 plat->deactivate_delay_us); 118 119 return 0; 120 } 121 122 static int tegra114_spi_probe(struct udevice *bus) 123 { 124 struct tegra_spi_platdata *plat = dev_get_platdata(bus); 125 struct tegra114_spi_priv *priv = dev_get_priv(bus); 126 struct spi_regs *regs; 127 ulong rate; 128 129 priv->regs = (struct spi_regs *)plat->base; 130 regs = priv->regs; 131 132 priv->last_transaction_us = timer_get_us(); 133 priv->freq = plat->frequency; 134 priv->periph_id = plat->periph_id; 135 136 /* 137 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling 138 * back to the oscillator if that is too fast. 139 */ 140 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 141 priv->freq); 142 if (rate > priv->freq + 100000) { 143 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC, 144 priv->freq); 145 if (rate != priv->freq) { 146 printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n", 147 bus->name, priv->freq, rate); 148 } 149 } 150 udelay(plat->deactivate_delay_us); 151 152 /* Clear stale status here */ 153 setbits_le32(®s->fifo_status, 154 SPI_FIFO_STS_ERR | 155 SPI_FIFO_STS_TX_FIFO_OVF | 156 SPI_FIFO_STS_TX_FIFO_UNR | 157 SPI_FIFO_STS_RX_FIFO_OVF | 158 SPI_FIFO_STS_RX_FIFO_UNR | 159 SPI_FIFO_STS_TX_FIFO_FULL | 160 SPI_FIFO_STS_TX_FIFO_EMPTY | 161 SPI_FIFO_STS_RX_FIFO_FULL | 162 SPI_FIFO_STS_RX_FIFO_EMPTY); 163 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); 164 165 setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | 166 (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL); 167 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); 168 169 return 0; 170 } 171 172 /** 173 * Activate the CS by driving it LOW 174 * 175 * @param slave Pointer to spi_slave to which controller has to 176 * communicate with 177 */ 178 static void spi_cs_activate(struct udevice *dev) 179 { 180 struct udevice *bus = dev->parent; 181 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 182 struct tegra114_spi_priv *priv = dev_get_priv(bus); 183 184 /* If it's too soon to do another transaction, wait */ 185 if (pdata->deactivate_delay_us && 186 priv->last_transaction_us) { 187 ulong delay_us; /* The delay completed so far */ 188 delay_us = timer_get_us() - priv->last_transaction_us; 189 if (delay_us < pdata->deactivate_delay_us) 190 udelay(pdata->deactivate_delay_us - delay_us); 191 } 192 193 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); 194 } 195 196 /** 197 * Deactivate the CS by driving it HIGH 198 * 199 * @param slave Pointer to spi_slave to which controller has to 200 * communicate with 201 */ 202 static void spi_cs_deactivate(struct udevice *dev) 203 { 204 struct udevice *bus = dev->parent; 205 struct tegra_spi_platdata *pdata = dev_get_platdata(bus); 206 struct tegra114_spi_priv *priv = dev_get_priv(bus); 207 208 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); 209 210 /* Remember time of this transaction so we can honour the bus delay */ 211 if (pdata->deactivate_delay_us) 212 priv->last_transaction_us = timer_get_us(); 213 214 debug("Deactivate CS, bus '%s'\n", bus->name); 215 } 216 217 static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, 218 const void *data_out, void *data_in, 219 unsigned long flags) 220 { 221 struct udevice *bus = dev->parent; 222 struct tegra114_spi_priv *priv = dev_get_priv(bus); 223 struct spi_regs *regs = priv->regs; 224 u32 reg, tmpdout, tmpdin = 0; 225 const u8 *dout = data_out; 226 u8 *din = data_in; 227 int num_bytes; 228 int ret; 229 230 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 231 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); 232 if (bitlen % 8) 233 return -1; 234 num_bytes = bitlen / 8; 235 236 ret = 0; 237 238 if (flags & SPI_XFER_BEGIN) 239 spi_cs_activate(dev); 240 241 /* clear all error status bits */ 242 reg = readl(®s->fifo_status); 243 writel(reg, ®s->fifo_status); 244 245 clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, 246 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | 247 (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT)); 248 249 /* set xfer size to 1 block (32 bits) */ 250 writel(0, ®s->dma_blk); 251 252 /* handle data in 32-bit chunks */ 253 while (num_bytes > 0) { 254 int bytes; 255 int tm, i; 256 257 tmpdout = 0; 258 bytes = (num_bytes > 4) ? 4 : num_bytes; 259 260 if (dout != NULL) { 261 for (i = 0; i < bytes; ++i) 262 tmpdout = (tmpdout << 8) | dout[i]; 263 dout += bytes; 264 } 265 266 num_bytes -= bytes; 267 268 /* clear ready bit */ 269 setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); 270 271 clrsetbits_le32(®s->command1, 272 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, 273 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); 274 writel(tmpdout, ®s->tx_fifo); 275 setbits_le32(®s->command1, SPI_CMD1_GO); 276 277 /* 278 * Wait for SPI transmit FIFO to empty, or to time out. 279 * The RX FIFO status will be read and cleared last 280 */ 281 for (tm = 0; tm < SPI_TIMEOUT; ++tm) { 282 u32 fifo_status, xfer_status; 283 284 xfer_status = readl(®s->xfer_status); 285 if (!(xfer_status & SPI_XFER_STS_RDY)) 286 continue; 287 288 fifo_status = readl(®s->fifo_status); 289 if (fifo_status & SPI_FIFO_STS_ERR) { 290 debug("%s: got a fifo error: ", __func__); 291 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) 292 debug("tx FIFO overflow "); 293 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) 294 debug("tx FIFO underrun "); 295 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) 296 debug("rx FIFO overflow "); 297 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) 298 debug("rx FIFO underrun "); 299 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) 300 debug("tx FIFO full "); 301 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) 302 debug("tx FIFO empty "); 303 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) 304 debug("rx FIFO full "); 305 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) 306 debug("rx FIFO empty "); 307 debug("\n"); 308 break; 309 } 310 311 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { 312 tmpdin = readl(®s->rx_fifo); 313 314 /* swap bytes read in */ 315 if (din != NULL) { 316 for (i = bytes - 1; i >= 0; --i) { 317 din[i] = tmpdin & 0xff; 318 tmpdin >>= 8; 319 } 320 din += bytes; 321 } 322 323 /* We can exit when we've had both RX and TX */ 324 break; 325 } 326 } 327 328 if (tm >= SPI_TIMEOUT) 329 ret = tm; 330 331 /* clear ACK RDY, etc. bits */ 332 writel(readl(®s->fifo_status), ®s->fifo_status); 333 } 334 335 if (flags & SPI_XFER_END) 336 spi_cs_deactivate(dev); 337 338 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", 339 __func__, tmpdin, readl(®s->fifo_status)); 340 341 if (ret) { 342 printf("%s: timeout during SPI transfer, tm %d\n", 343 __func__, ret); 344 return -1; 345 } 346 347 return ret; 348 } 349 350 static int tegra114_spi_set_speed(struct udevice *bus, uint speed) 351 { 352 struct tegra_spi_platdata *plat = bus->platdata; 353 struct tegra114_spi_priv *priv = dev_get_priv(bus); 354 355 if (speed > plat->frequency) 356 speed = plat->frequency; 357 priv->freq = speed; 358 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 359 360 return 0; 361 } 362 363 static int tegra114_spi_set_mode(struct udevice *bus, uint mode) 364 { 365 struct tegra114_spi_priv *priv = dev_get_priv(bus); 366 367 priv->mode = mode; 368 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 369 370 return 0; 371 } 372 373 static const struct dm_spi_ops tegra114_spi_ops = { 374 .xfer = tegra114_spi_xfer, 375 .set_speed = tegra114_spi_set_speed, 376 .set_mode = tegra114_spi_set_mode, 377 /* 378 * cs_info is not needed, since we require all chip selects to be 379 * in the device tree explicitly 380 */ 381 }; 382 383 static const struct udevice_id tegra114_spi_ids[] = { 384 { .compatible = "nvidia,tegra114-spi" }, 385 { } 386 }; 387 388 U_BOOT_DRIVER(tegra114_spi) = { 389 .name = "tegra114_spi", 390 .id = UCLASS_SPI, 391 .of_match = tegra114_spi_ids, 392 .ops = &tegra114_spi_ops, 393 .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata, 394 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), 395 .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv), 396 .probe = tegra114_spi_probe, 397 }; 398