1 /* 2 * (C) Copyright 2016 Carlo Caione <carlo@caione.org> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <mmc.h> 12 #include <asm/io.h> 13 #include <asm/arch/sd_emmc.h> 14 #include <linux/log2.h> 15 16 static inline void *get_regbase(const struct mmc *mmc) 17 { 18 struct meson_mmc_platdata *pdata = mmc->priv; 19 20 return pdata->regbase; 21 } 22 23 static inline uint32_t meson_read(struct mmc *mmc, int offset) 24 { 25 return readl(get_regbase(mmc) + offset); 26 } 27 28 static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) 29 { 30 writel(val, get_regbase(mmc) + offset); 31 } 32 33 static void meson_mmc_config_clock(struct mmc *mmc) 34 { 35 uint32_t meson_mmc_clk = 0; 36 unsigned int clk, clk_src, clk_div; 37 38 if (!mmc->clock) 39 return; 40 41 /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ 42 if (mmc->clock > 16000000) { 43 clk = SD_EMMC_CLKSRC_DIV2; 44 clk_src = CLK_SRC_DIV2; 45 } else { 46 clk = SD_EMMC_CLKSRC_24M; 47 clk_src = CLK_SRC_24M; 48 } 49 clk_div = DIV_ROUND_UP(clk, mmc->clock); 50 51 /* 180 phase core clock */ 52 meson_mmc_clk |= CLK_CO_PHASE_180; 53 54 /* 180 phase tx clock */ 55 meson_mmc_clk |= CLK_TX_PHASE_000; 56 57 /* clock settings */ 58 meson_mmc_clk |= clk_src; 59 meson_mmc_clk |= clk_div; 60 61 meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK); 62 } 63 64 static int meson_dm_mmc_set_ios(struct udevice *dev) 65 { 66 struct mmc *mmc = mmc_get_mmc_dev(dev); 67 uint32_t meson_mmc_cfg; 68 69 meson_mmc_config_clock(mmc); 70 71 meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG); 72 73 meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK; 74 if (mmc->bus_width == 1) 75 meson_mmc_cfg |= CFG_BUS_WIDTH_1; 76 else if (mmc->bus_width == 4) 77 meson_mmc_cfg |= CFG_BUS_WIDTH_4; 78 else if (mmc->bus_width == 8) 79 meson_mmc_cfg |= CFG_BUS_WIDTH_8; 80 else 81 return -EINVAL; 82 83 /* 512 bytes block length */ 84 meson_mmc_cfg &= ~CFG_BL_LEN_MASK; 85 meson_mmc_cfg |= CFG_BL_LEN_512; 86 87 /* Response timeout 256 clk */ 88 meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK; 89 meson_mmc_cfg |= CFG_RESP_TIMEOUT_256; 90 91 /* Command-command gap 16 clk */ 92 meson_mmc_cfg &= ~CFG_RC_CC_MASK; 93 meson_mmc_cfg |= CFG_RC_CC_16; 94 95 meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG); 96 97 return 0; 98 } 99 100 static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data, 101 struct mmc_cmd *cmd) 102 { 103 uint32_t meson_mmc_cmd = 0, cfg; 104 105 meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT; 106 107 if (cmd->resp_type & MMC_RSP_PRESENT) { 108 if (cmd->resp_type & MMC_RSP_136) 109 meson_mmc_cmd |= CMD_CFG_RESP_128; 110 111 if (cmd->resp_type & MMC_RSP_BUSY) 112 meson_mmc_cmd |= CMD_CFG_R1B; 113 114 if (!(cmd->resp_type & MMC_RSP_CRC)) 115 meson_mmc_cmd |= CMD_CFG_RESP_NOCRC; 116 } else { 117 meson_mmc_cmd |= CMD_CFG_NO_RESP; 118 } 119 120 if (data) { 121 cfg = meson_read(mmc, MESON_SD_EMMC_CFG); 122 cfg &= ~CFG_BL_LEN_MASK; 123 cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT; 124 meson_write(mmc, cfg, MESON_SD_EMMC_CFG); 125 126 if (data->flags == MMC_DATA_WRITE) 127 meson_mmc_cmd |= CMD_CFG_DATA_WR; 128 129 meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE | 130 data->blocks; 131 } 132 133 meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER | 134 CMD_CFG_END_OF_CHAIN; 135 136 meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG); 137 } 138 139 static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data) 140 { 141 struct meson_mmc_platdata *pdata = mmc->priv; 142 unsigned int data_size; 143 uint32_t data_addr = 0; 144 145 if (data) { 146 data_size = data->blocks * data->blocksize; 147 148 if (data->flags == MMC_DATA_READ) { 149 data_addr = (ulong) data->dest; 150 invalidate_dcache_range(data_addr, 151 data_addr + data_size); 152 } else { 153 pdata->w_buf = calloc(data_size, sizeof(char)); 154 data_addr = (ulong) pdata->w_buf; 155 memcpy(pdata->w_buf, data->src, data_size); 156 flush_dcache_range(data_addr, data_addr + data_size); 157 } 158 } 159 160 meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT); 161 } 162 163 static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd) 164 { 165 if (cmd->resp_type & MMC_RSP_136) { 166 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3); 167 cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2); 168 cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1); 169 cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); 170 } else { 171 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); 172 } 173 } 174 175 static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 176 struct mmc_data *data) 177 { 178 struct mmc *mmc = mmc_get_mmc_dev(dev); 179 struct meson_mmc_platdata *pdata = mmc->priv; 180 uint32_t status; 181 ulong start; 182 int ret = 0; 183 184 /* max block size supported by chip is 512 byte */ 185 if (data && data->blocksize > 512) 186 return -EINVAL; 187 188 meson_mmc_setup_cmd(mmc, data, cmd); 189 meson_mmc_setup_addr(mmc, data); 190 191 meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG); 192 193 /* use 10s timeout */ 194 start = get_timer(0); 195 do { 196 status = meson_read(mmc, MESON_SD_EMMC_STATUS); 197 } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000); 198 199 if (!(status & STATUS_END_OF_CHAIN)) 200 ret = -ETIMEDOUT; 201 else if (status & STATUS_RESP_TIMEOUT) 202 ret = -ETIMEDOUT; 203 else if (status & STATUS_ERR_MASK) 204 ret = -EIO; 205 206 meson_mmc_read_response(mmc, cmd); 207 208 if (data && data->flags == MMC_DATA_WRITE) 209 free(pdata->w_buf); 210 211 /* reset status bits */ 212 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); 213 214 return ret; 215 } 216 217 static const struct dm_mmc_ops meson_dm_mmc_ops = { 218 .send_cmd = meson_dm_mmc_send_cmd, 219 .set_ios = meson_dm_mmc_set_ios, 220 }; 221 222 static int meson_mmc_ofdata_to_platdata(struct udevice *dev) 223 { 224 struct meson_mmc_platdata *pdata = dev_get_platdata(dev); 225 fdt_addr_t addr; 226 227 addr = devfdt_get_addr(dev); 228 if (addr == FDT_ADDR_T_NONE) 229 return -EINVAL; 230 231 pdata->regbase = (void *)addr; 232 233 return 0; 234 } 235 236 static int meson_mmc_probe(struct udevice *dev) 237 { 238 struct meson_mmc_platdata *pdata = dev_get_platdata(dev); 239 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 240 struct mmc *mmc = &pdata->mmc; 241 struct mmc_config *cfg = &pdata->cfg; 242 uint32_t val; 243 244 cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | 245 MMC_VDD_31_32 | MMC_VDD_165_195; 246 cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | 247 MMC_MODE_HS_52MHz | MMC_MODE_HS; 248 cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); 249 cfg->f_max = 100000000; /* 100 MHz */ 250 cfg->b_max = 511; /* max 512 - 1 blocks */ 251 cfg->name = dev->name; 252 253 mmc->priv = pdata; 254 upriv->mmc = mmc; 255 256 mmc_set_clock(mmc, cfg->f_min, false); 257 258 /* reset all status bits */ 259 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); 260 261 /* disable interrupts */ 262 meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN); 263 264 /* enable auto clock mode */ 265 val = meson_read(mmc, MESON_SD_EMMC_CFG); 266 val &= ~CFG_SDCLK_ALWAYS_ON; 267 val |= CFG_AUTO_CLK; 268 meson_write(mmc, val, MESON_SD_EMMC_CFG); 269 270 return 0; 271 } 272 273 int meson_mmc_bind(struct udevice *dev) 274 { 275 struct meson_mmc_platdata *pdata = dev_get_platdata(dev); 276 277 return mmc_bind(dev, &pdata->mmc, &pdata->cfg); 278 } 279 280 static const struct udevice_id meson_mmc_match[] = { 281 { .compatible = "amlogic,meson-gx-mmc" }, 282 { /* sentinel */ } 283 }; 284 285 U_BOOT_DRIVER(meson_mmc) = { 286 .name = "meson_gx_mmc", 287 .id = UCLASS_MMC, 288 .of_match = meson_mmc_match, 289 .ops = &meson_dm_mmc_ops, 290 .probe = meson_mmc_probe, 291 .bind = meson_mmc_bind, 292 .ofdata_to_platdata = meson_mmc_ofdata_to_platdata, 293 .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata), 294 }; 295