1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 17 #define CONFIG_MPC837XERDB 1 18 19 #define CONFIG_MISC_INIT_R 20 #define CONFIG_HWCONFIG 21 22 /* 23 * On-board devices 24 */ 25 #define CONFIG_VSC7385_ENET 26 27 /* 28 * System Clock Setup 29 */ 30 #ifdef CONFIG_PCISLAVE 31 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 32 #else 33 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 34 #define CONFIG_PCIE 35 #endif 36 37 #ifndef CONFIG_SYS_CLK_FREQ 38 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 39 #endif 40 41 /* 42 * Hardware Reset Configuration Word 43 */ 44 #define CONFIG_SYS_HRCW_LOW (\ 45 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 46 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 47 HRCWL_SVCOD_DIV_2 |\ 48 HRCWL_CSB_TO_CLKIN_5X1 |\ 49 HRCWL_CORE_TO_CSB_2X1) 50 51 #ifdef CONFIG_PCISLAVE 52 #define CONFIG_SYS_HRCW_HIGH (\ 53 HRCWH_PCI_AGENT |\ 54 HRCWH_PCI1_ARBITER_DISABLE |\ 55 HRCWH_CORE_ENABLE |\ 56 HRCWH_FROM_0XFFF00100 |\ 57 HRCWH_BOOTSEQ_DISABLE |\ 58 HRCWH_SW_WATCHDOG_DISABLE |\ 59 HRCWH_ROM_LOC_LOCAL_16BIT |\ 60 HRCWH_RL_EXT_LEGACY |\ 61 HRCWH_TSEC1M_IN_RGMII |\ 62 HRCWH_TSEC2M_IN_RGMII |\ 63 HRCWH_BIG_ENDIAN |\ 64 HRCWH_LDP_CLEAR) 65 #else 66 #define CONFIG_SYS_HRCW_HIGH (\ 67 HRCWH_PCI_HOST |\ 68 HRCWH_PCI1_ARBITER_ENABLE |\ 69 HRCWH_CORE_ENABLE |\ 70 HRCWH_FROM_0X00000100 |\ 71 HRCWH_BOOTSEQ_DISABLE |\ 72 HRCWH_SW_WATCHDOG_DISABLE |\ 73 HRCWH_ROM_LOC_LOCAL_16BIT |\ 74 HRCWH_RL_EXT_LEGACY |\ 75 HRCWH_TSEC1M_IN_RGMII |\ 76 HRCWH_TSEC2M_IN_RGMII |\ 77 HRCWH_BIG_ENDIAN |\ 78 HRCWH_LDP_CLEAR) 79 #endif 80 81 /* System performance - define the value i.e. CONFIG_SYS_XXX 82 */ 83 84 /* Arbiter Configuration Register */ 85 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 86 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 87 88 /* System Priority Control Regsiter */ 89 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 90 91 /* System Clock Configuration Register */ 92 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 93 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 94 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 95 96 /* 97 * System IO Config 98 */ 99 #define CONFIG_SYS_SICRH 0x08200000 100 #define CONFIG_SYS_SICRL 0x00000000 101 102 /* 103 * Output Buffer Impedance 104 */ 105 #define CONFIG_SYS_OBIR 0x30100000 106 107 /* 108 * IMMR new address 109 */ 110 #define CONFIG_SYS_IMMR 0xE0000000 111 112 /* 113 * Device configurations 114 */ 115 116 /* Vitesse 7385 */ 117 118 #ifdef CONFIG_VSC7385_ENET 119 120 #define CONFIG_TSEC2 121 122 /* The flash address and size of the VSC7385 firmware image */ 123 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 124 #define CONFIG_VSC7385_IMAGE_SIZE 8192 125 126 #endif 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 133 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 134 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 135 #define CONFIG_SYS_83XX_DDR_USES_CS0 136 137 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 138 139 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 140 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 141 142 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 143 144 /* 145 * Manually set up DDR parameters 146 */ 147 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 148 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 149 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 150 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 151 | CSCONFIG_ROW_BIT_13 \ 152 | CSCONFIG_COL_BIT_10) 153 154 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 155 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 156 | (0 << TIMING_CFG0_WRT_SHIFT) \ 157 | (0 << TIMING_CFG0_RRT_SHIFT) \ 158 | (0 << TIMING_CFG0_WWT_SHIFT) \ 159 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 160 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 161 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 162 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 163 /* 0x00260802 */ /* DDR400 */ 164 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 165 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 166 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 167 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 168 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 169 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 170 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 171 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 172 /* 0x3937d322 */ 173 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 174 | (5 << TIMING_CFG2_CPO_SHIFT) \ 175 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 176 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 177 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 178 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 179 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 180 /* 0x02984cc8 */ 181 182 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 183 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 184 /* 0x06090100 */ 185 186 #if defined(CONFIG_DDR_2T_TIMING) 187 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 188 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 189 | SDRAM_CFG_32_BE \ 190 | SDRAM_CFG_2T_EN) 191 /* 0x43088000 */ 192 #else 193 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 194 | SDRAM_CFG_SDRAM_TYPE_DDR2) 195 /* 0x43000000 */ 196 #endif 197 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 198 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 199 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 200 /* 0x04400442 */ /* DDR400 */ 201 #define CONFIG_SYS_DDR_MODE2 0x00000000 202 203 /* 204 * Memory test 205 */ 206 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 207 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 208 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 209 210 /* 211 * The reserved memory 212 */ 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 214 215 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 216 #define CONFIG_SYS_RAMBOOT 217 #else 218 #undef CONFIG_SYS_RAMBOOT 219 #endif 220 221 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 222 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 223 224 /* 225 * Initial RAM Base Address Setup 226 */ 227 #define CONFIG_SYS_INIT_RAM_LOCK 1 228 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 230 #define CONFIG_SYS_GBL_DATA_OFFSET \ 231 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 232 233 /* 234 * Local Bus Configuration & Clock Setup 235 */ 236 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 237 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 238 #define CONFIG_SYS_LBC_LBCR 0x00000000 239 #define CONFIG_FSL_ELBC 1 240 241 /* 242 * FLASH on the Local Bus 243 */ 244 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 245 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 246 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 247 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 248 249 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 250 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 251 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 252 253 /* Window base at flash base */ 254 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 255 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 256 257 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 258 | BR_PS_16 /* 16 bit port */ \ 259 | BR_MS_GPCM /* MSEL = GPCM */ \ 260 | BR_V) /* valid */ 261 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 262 | OR_GPCM_XACS \ 263 | OR_GPCM_SCY_9 \ 264 | OR_GPCM_EHTR_SET \ 265 | OR_GPCM_EAD) 266 /* 0xFF800191 */ 267 268 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 269 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 270 271 #undef CONFIG_SYS_FLASH_CHECKSUM 272 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 273 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 274 275 /* 276 * NAND Flash on the Local Bus 277 */ 278 #define CONFIG_SYS_NAND_BASE 0xE0600000 279 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 280 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 281 | BR_PS_8 /* 8 bit port */ \ 282 | BR_MS_FCM /* MSEL = FCM */ \ 283 | BR_V) /* valid */ 284 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 285 | OR_FCM_CSCT \ 286 | OR_FCM_CST \ 287 | OR_FCM_CHT \ 288 | OR_FCM_SCY_1 \ 289 | OR_FCM_TRLX \ 290 | OR_FCM_EHTR) 291 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 292 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 293 294 /* Vitesse 7385 */ 295 296 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 297 298 #ifdef CONFIG_VSC7385_ENET 299 300 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 301 | BR_PS_8 \ 302 | BR_MS_GPCM \ 303 | BR_V) 304 /* 0xF0000801 */ 305 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 306 | OR_GPCM_CSNT \ 307 | OR_GPCM_XACS \ 308 | OR_GPCM_SCY_15 \ 309 | OR_GPCM_SETA \ 310 | OR_GPCM_TRLX_SET \ 311 | OR_GPCM_EHTR_SET \ 312 | OR_GPCM_EAD) 313 /* 0xfffe09ff */ 314 315 /* Access Base */ 316 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 317 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 318 319 #endif 320 321 /* 322 * Serial Port 323 */ 324 #define CONFIG_SYS_NS16550_SERIAL 325 #define CONFIG_SYS_NS16550_REG_SIZE 1 326 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 333 334 /* SERDES */ 335 #define CONFIG_FSL_SERDES 336 #define CONFIG_FSL_SERDES1 0xe3000 337 #define CONFIG_FSL_SERDES2 0xe3100 338 339 /* I2C */ 340 #define CONFIG_SYS_I2C 341 #define CONFIG_SYS_I2C_FSL 342 #define CONFIG_SYS_FSL_I2C_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 344 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 345 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 346 347 /* 348 * Config on-board RTC 349 */ 350 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 351 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 352 353 /* 354 * General PCI 355 * Addresses are mapped 1-1. 356 */ 357 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 358 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 359 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 360 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 361 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 362 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 363 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 364 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 365 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 366 367 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 368 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 369 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 370 371 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 372 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 373 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 374 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 375 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 376 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 377 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 378 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 379 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 380 381 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 382 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 383 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 384 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 385 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 386 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 387 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 388 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 389 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 390 391 #ifdef CONFIG_PCI 392 #define CONFIG_PCI_INDIRECT_BRIDGE 393 394 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 395 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 396 #endif /* CONFIG_PCI */ 397 398 /* 399 * TSEC 400 */ 401 #ifdef CONFIG_TSEC_ENET 402 403 #define CONFIG_GMII /* MII PHY management */ 404 405 #define CONFIG_TSEC1 406 407 #ifdef CONFIG_TSEC1 408 #define CONFIG_HAS_ETH0 409 #define CONFIG_TSEC1_NAME "TSEC0" 410 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 411 #define TSEC1_PHY_ADDR 2 412 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 413 #define TSEC1_PHYIDX 0 414 #endif 415 416 #ifdef CONFIG_TSEC2 417 #define CONFIG_HAS_ETH1 418 #define CONFIG_TSEC2_NAME "TSEC1" 419 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 420 #define TSEC2_PHY_ADDR 0x1c 421 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 422 #define TSEC2_PHYIDX 0 423 #endif 424 425 /* Options are: TSEC[0-1] */ 426 #define CONFIG_ETHPRIME "TSEC0" 427 428 #endif 429 430 /* 431 * SATA 432 */ 433 #define CONFIG_SYS_SATA_MAX_DEVICE 2 434 #define CONFIG_SATA1 435 #define CONFIG_SYS_SATA1_OFFSET 0x18000 436 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 437 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 438 #define CONFIG_SATA2 439 #define CONFIG_SYS_SATA2_OFFSET 0x19000 440 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 441 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 442 443 #ifdef CONFIG_FSL_SATA 444 #define CONFIG_LBA48 445 #endif 446 447 /* 448 * Environment 449 */ 450 #ifndef CONFIG_SYS_RAMBOOT 451 #define CONFIG_ENV_ADDR \ 452 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 453 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 454 #define CONFIG_ENV_SIZE 0x4000 455 #else 456 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 457 #define CONFIG_ENV_SIZE 0x2000 458 #endif 459 460 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 461 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 462 463 /* 464 * BOOTP options 465 */ 466 #define CONFIG_BOOTP_BOOTFILESIZE 467 468 /* 469 * Command line configuration. 470 */ 471 472 #undef CONFIG_WATCHDOG /* watchdog disabled */ 473 474 #ifdef CONFIG_MMC 475 #define CONFIG_FSL_ESDHC_PIN_MUX 476 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 477 #endif 478 479 /* 480 * Miscellaneous configurable options 481 */ 482 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 483 484 /* 485 * For booting Linux, the board info and command line data 486 * have to be in the first 256 MB of memory, since this is 487 * the maximum mapped by the Linux kernel during initialization. 488 */ 489 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 490 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 491 492 /* 493 * Core HID Setup 494 */ 495 #define CONFIG_SYS_HID0_INIT 0x000000000 496 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 497 | HID0_ENABLE_INSTRUCTION_CACHE) 498 #define CONFIG_SYS_HID2 HID2_HBE 499 500 /* 501 * MMU Setup 502 */ 503 504 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 505 506 /* DDR: cache cacheable */ 507 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 508 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 509 510 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 511 | BATL_PP_RW \ 512 | BATL_MEMCOHERENCE) 513 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 514 | BATU_BL_256M \ 515 | BATU_VS \ 516 | BATU_VP) 517 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 518 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 519 520 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 521 | BATL_PP_RW \ 522 | BATL_MEMCOHERENCE) 523 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 524 | BATU_BL_256M \ 525 | BATU_VS \ 526 | BATU_VP) 527 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 528 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 529 530 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 531 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 532 | BATL_PP_RW \ 533 | BATL_CACHEINHIBIT \ 534 | BATL_GUARDEDSTORAGE) 535 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 536 | BATU_BL_8M \ 537 | BATU_VS \ 538 | BATU_VP) 539 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 540 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 541 542 /* L2 Switch: cache-inhibit and guarded */ 543 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ 544 | BATL_PP_RW \ 545 | BATL_CACHEINHIBIT \ 546 | BATL_GUARDEDSTORAGE) 547 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ 548 | BATU_BL_128K \ 549 | BATU_VS \ 550 | BATU_VP) 551 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 552 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 553 554 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 555 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 556 | BATL_PP_RW \ 557 | BATL_MEMCOHERENCE) 558 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 559 | BATU_BL_32M \ 560 | BATU_VS \ 561 | BATU_VP) 562 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 563 | BATL_PP_RW \ 564 | BATL_CACHEINHIBIT \ 565 | BATL_GUARDEDSTORAGE) 566 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 567 568 /* Stack in dcache: cacheable, no memory coherence */ 569 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 570 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 571 | BATU_BL_128K \ 572 | BATU_VS \ 573 | BATU_VP) 574 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 575 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 576 577 #ifdef CONFIG_PCI 578 /* PCI MEM space: cacheable */ 579 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 580 | BATL_PP_RW \ 581 | BATL_MEMCOHERENCE) 582 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 583 | BATU_BL_256M \ 584 | BATU_VS \ 585 | BATU_VP) 586 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 587 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 588 /* PCI MMIO space: cache-inhibit and guarded */ 589 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 590 | BATL_PP_RW \ 591 | BATL_CACHEINHIBIT \ 592 | BATL_GUARDEDSTORAGE) 593 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 594 | BATU_BL_256M \ 595 | BATU_VS \ 596 | BATU_VP) 597 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 598 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 599 #else 600 #define CONFIG_SYS_IBAT6L (0) 601 #define CONFIG_SYS_IBAT6U (0) 602 #define CONFIG_SYS_IBAT7L (0) 603 #define CONFIG_SYS_IBAT7U (0) 604 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 605 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 606 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 607 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 608 #endif 609 610 #if defined(CONFIG_CMD_KGDB) 611 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 612 #endif 613 614 /* 615 * Environment Configuration 616 */ 617 #define CONFIG_ENV_OVERWRITE 618 619 #define CONFIG_HAS_FSL_DR_USB 620 #define CONFIG_USB_EHCI_FSL 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 622 623 #define CONFIG_NETDEV "eth1" 624 625 #define CONFIG_HOSTNAME "mpc837x_rdb" 626 #define CONFIG_ROOTPATH "/nfsroot" 627 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 628 #define CONFIG_BOOTFILE "uImage" 629 /* U-Boot image on TFTP server */ 630 #define CONFIG_UBOOTPATH "u-boot.bin" 631 #define CONFIG_FDTFILE "mpc8379_rdb.dtb" 632 633 /* default location for tftp and bootm */ 634 #define CONFIG_LOADADDR 800000 635 636 #define CONFIG_EXTRA_ENV_SETTINGS \ 637 "netdev=" CONFIG_NETDEV "\0" \ 638 "uboot=" CONFIG_UBOOTPATH "\0" \ 639 "tftpflash=tftp $loadaddr $uboot;" \ 640 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 641 " +$filesize; " \ 642 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 643 " +$filesize; " \ 644 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 645 " $filesize; " \ 646 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 647 " +$filesize; " \ 648 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 649 " $filesize\0" \ 650 "fdtaddr=780000\0" \ 651 "fdtfile=" CONFIG_FDTFILE "\0" \ 652 "ramdiskaddr=1000000\0" \ 653 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 654 "console=ttyS0\0" \ 655 "setbootargs=setenv bootargs " \ 656 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 657 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 658 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 659 "$netdev:off " \ 660 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 661 662 #define CONFIG_NFSBOOTCOMMAND \ 663 "setenv rootdev /dev/nfs;" \ 664 "run setbootargs;" \ 665 "run setipargs;" \ 666 "tftp $loadaddr $bootfile;" \ 667 "tftp $fdtaddr $fdtfile;" \ 668 "bootm $loadaddr - $fdtaddr" 669 670 #define CONFIG_RAMBOOTCOMMAND \ 671 "setenv rootdev /dev/ram;" \ 672 "run setbootargs;" \ 673 "tftp $ramdiskaddr $ramdiskfile;" \ 674 "tftp $loadaddr $bootfile;" \ 675 "tftp $fdtaddr $fdtfile;" \ 676 "bootm $loadaddr $ramdiskaddr $fdtaddr" 677 678 #endif /* __CONFIG_H */ 679