1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Contributor: Mahavir Jain <mjain@marvell.com>
7 */
8
9 #include <common.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/armada100.h>
12
13 #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
14 #define SET_MRVL_ID (1<<8)
15 #define L2C_RAM_SEL (1<<4)
16
arch_cpu_init(void)17 int arch_cpu_init(void)
18 {
19 u32 val;
20 struct armd1cpu_registers *cpuregs =
21 (struct armd1cpu_registers *) ARMD1_CPU_BASE;
22
23 struct armd1apb1_registers *apb1clkres =
24 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
25
26 struct armd1mpmu_registers *mpmu =
27 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
28
29 /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
30 val = readl(&cpuregs->cpu_conf);
31 val = val | SET_MRVL_ID;
32 writel(val, &cpuregs->cpu_conf);
33
34 /* Enable Clocks for all hardware units */
35 writel(0xFFFFFFFF, &mpmu->acgr);
36
37 /* Turn on AIB and AIB-APB Functional clock */
38 writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
39
40 /* ensure L2 cache is not mapped as SRAM */
41 val = readl(&cpuregs->cpu_conf);
42 val = val & ~(L2C_RAM_SEL);
43 writel(val, &cpuregs->cpu_conf);
44
45 /* Enable GPIO clock */
46 writel(APBC_APBCLK, &apb1clkres->gpio);
47
48 #ifdef CONFIG_I2C_MV
49 /* Enable general I2C clock */
50 writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
51 writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
52
53 /* Enable power I2C clock */
54 writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
55 writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
56 #endif
57
58 /*
59 * Enable Functional and APB clock at 14.7456MHz
60 * for configured UART console
61 */
62 #if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
63 writel(UARTCLK14745KHZ, &apb1clkres->uart3);
64 #elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
65 writel(UARTCLK14745KHZ, &apb1clkres->uart2);
66 #else
67 writel(UARTCLK14745KHZ, &apb1clkres->uart1);
68 #endif
69 icache_enable();
70
71 return 0;
72 }
73
74 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)75 int print_cpuinfo(void)
76 {
77 u32 id;
78 struct armd1cpu_registers *cpuregs =
79 (struct armd1cpu_registers *) ARMD1_CPU_BASE;
80
81 id = readl(&cpuregs->chip_id);
82 printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
83 return 0;
84 }
85 #endif
86
87 #ifdef CONFIG_I2C_MV
i2c_clk_enable(void)88 void i2c_clk_enable(void)
89 {
90 }
91 #endif
92