1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2015 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <linux/errno.h> 12 #include <asm/io.h> 13 #include <asm-generic/gpio.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch-tegra/usb.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <usb.h> 18 #include <usb/ulpi.h> 19 #include <linux/libfdt.h> 20 21 #include "ehci.h" 22 23 #define USB1_ADDR_MASK 0xFFFF0000 24 25 #define HOSTPC1_DEVLC 0x84 26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 27 28 #ifdef CONFIG_USB_ULPI 29 #ifndef CONFIG_USB_ULPI_VIEWPORT 30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 31 define CONFIG_USB_ULPI_VIEWPORT" 32 #endif 33 #endif 34 35 /* Parameters we need for USB */ 36 enum { 37 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 38 PARAM_DIVM, /* PLL INPUT DIVIDER */ 39 PARAM_DIVP, /* POST DIVIDER (2^N) */ 40 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 41 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 42 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 43 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 44 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 45 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 46 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 47 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 48 49 PARAM_COUNT 50 }; 51 52 /* Possible port types (dual role mode) */ 53 enum dr_mode { 54 DR_MODE_NONE = 0, 55 DR_MODE_HOST, /* supports host operation */ 56 DR_MODE_DEVICE, /* supports device operation */ 57 DR_MODE_OTG, /* supports both */ 58 }; 59 60 enum usb_ctlr_type { 61 USB_CTLR_T20, 62 USB_CTLR_T30, 63 USB_CTLR_T114, 64 USB_CTLR_T210, 65 66 USB_CTRL_COUNT, 67 }; 68 69 /* Information about a USB port */ 70 struct fdt_usb { 71 struct ehci_ctrl ehci; 72 struct usb_ctlr *reg; /* address of registers in physical memory */ 73 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 74 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 75 unsigned enabled:1; /* 1 to enable, 0 to disable */ 76 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 77 enum usb_ctlr_type type; 78 enum usb_init_type init_type; 79 enum dr_mode dr_mode; /* dual role mode */ 80 enum periph_id periph_id;/* peripheral id */ 81 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 82 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 83 }; 84 85 /* 86 * This table has USB timing parameters for each Oscillator frequency we 87 * support. There are four sets of values: 88 * 89 * 1. PLLU configuration information (reference clock is osc/clk_m and 90 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 91 * 92 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 93 * ---------------------------------------------------------------------- 94 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 95 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 96 * Filter frequency (MHz) 1 4.8 6 2 97 * CPCON 1100b 0011b 1100b 1100b 98 * LFCON0 0 0 0 0 99 * 100 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 101 * 102 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 103 * --------------------------------------------------------------------------- 104 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 105 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 106 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 107 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 108 * 109 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 110 * SessEnd. Each of these signals have their own debouncer and for each of 111 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 112 * BIAS_DEBOUNCE_B). 113 * 114 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 115 * 0xffff -> No debouncing at all 116 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 117 * 118 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 119 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 120 * 121 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 122 * values, so we can keep those to default. 123 * 124 * 4. The 20 microsecond delay after bias cell operation. 125 */ 126 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 127 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 128 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 129 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 130 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 131 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, 132 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 133 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } 134 }; 135 136 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 137 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 138 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 139 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 140 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 141 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, 142 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 143 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } 144 }; 145 146 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 147 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 148 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 149 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 150 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 151 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 }, 152 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 153 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } 154 }; 155 156 /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ 157 static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 158 /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ 159 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, 160 { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, 161 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, 162 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }, 163 { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, 164 { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 } 165 }; 166 167 /* UTMIP Idle Wait Delay */ 168 static const u8 utmip_idle_wait_delay = 17; 169 170 /* UTMIP Elastic limit */ 171 static const u8 utmip_elastic_limit = 16; 172 173 /* UTMIP High Speed Sync Start Delay */ 174 static const u8 utmip_hs_sync_start_delay = 9; 175 176 struct fdt_usb_controller { 177 /* flag to determine whether controller supports hostpc register */ 178 u32 has_hostpc:1; 179 const unsigned *pll_parameter; 180 }; 181 182 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 183 { 184 .has_hostpc = 0, 185 .pll_parameter = (const unsigned *)T20_usb_pll, 186 }, 187 { 188 .has_hostpc = 1, 189 .pll_parameter = (const unsigned *)T30_usb_pll, 190 }, 191 { 192 .has_hostpc = 1, 193 .pll_parameter = (const unsigned *)T114_usb_pll, 194 }, 195 { 196 .has_hostpc = 1, 197 .pll_parameter = (const unsigned *)T210_usb_pll, 198 }, 199 }; 200 201 /* 202 * A known hardware issue where Connect Status Change bit of PORTSC register 203 * of USB1 controller will be set after Port Reset. 204 * We have to clear it in order for later device enumeration to proceed. 205 */ 206 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 207 uint32_t *status_reg, uint32_t *reg) 208 { 209 struct fdt_usb *config = ctrl->priv; 210 struct fdt_usb_controller *controller; 211 212 controller = &fdt_usb_controllers[config->type]; 213 mdelay(50); 214 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 215 if (controller->has_hostpc) 216 *reg |= EHCI_PS_PE; 217 218 if (!config->has_legacy_mode) 219 return; 220 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 221 if (ehci_readl(status_reg) & EHCI_PS_CSC) 222 *reg |= EHCI_PS_CSC; 223 } 224 225 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 226 { 227 struct fdt_usb *config = ctrl->priv; 228 struct usb_ctlr *usbctlr; 229 uint32_t tmp; 230 231 usbctlr = config->reg; 232 233 tmp = ehci_readl(&usbctlr->usb_mode); 234 tmp |= USBMODE_CM_HC; 235 ehci_writel(&usbctlr->usb_mode, tmp); 236 } 237 238 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 239 { 240 struct fdt_usb *config = ctrl->priv; 241 struct fdt_usb_controller *controller; 242 uint32_t tmp; 243 uint32_t *reg_ptr; 244 245 controller = &fdt_usb_controllers[config->type]; 246 if (controller->has_hostpc) { 247 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 248 HOSTPC1_DEVLC); 249 tmp = ehci_readl(reg_ptr); 250 return HOSTPC1_PSPD(tmp); 251 } else 252 return PORTSC_PSPD(reg); 253 } 254 255 /* Set up VBUS for host/device mode */ 256 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 257 { 258 /* 259 * If we are an OTG port initializing in host mode, 260 * check if remote host is driving VBus and bail out in this case. 261 */ 262 if (init == USB_INIT_HOST && 263 config->dr_mode == DR_MODE_OTG && 264 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 265 printf("tegrausb: VBUS input active; not enabling as host\n"); 266 return; 267 } 268 269 if (dm_gpio_is_valid(&config->vbus_gpio)) { 270 int vbus_value; 271 272 vbus_value = (init == USB_INIT_HOST); 273 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 274 275 debug("set_up_vbus: GPIO %d %d\n", 276 gpio_get_number(&config->vbus_gpio), vbus_value); 277 } 278 } 279 280 static void usbf_reset_controller(struct fdt_usb *config, 281 struct usb_ctlr *usbctlr) 282 { 283 /* Reset the USB controller with 2us delay */ 284 reset_periph(config->periph_id, 2); 285 286 /* 287 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 288 * base address 289 */ 290 if (config->has_legacy_mode) 291 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 292 293 /* Put UTMIP1/3 in reset */ 294 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 295 296 /* Enable the UTMIP PHY */ 297 if (config->utmi) 298 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 299 } 300 301 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 302 { 303 const unsigned *timing; 304 305 timing = controller->pll_parameter + 306 clock_get_osc_freq() * PARAM_COUNT; 307 308 return timing; 309 } 310 311 /* select the PHY to use with a USB controller */ 312 static void init_phy_mux(struct fdt_usb *config, uint pts, 313 enum usb_init_type init) 314 { 315 struct usb_ctlr *usbctlr = config->reg; 316 317 #if defined(CONFIG_TEGRA20) 318 if (config->periph_id == PERIPH_ID_USBD) { 319 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 320 pts << PTS1_SHIFT); 321 clrbits_le32(&usbctlr->port_sc1, STS1); 322 } else { 323 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 324 pts << PTS_SHIFT); 325 clrbits_le32(&usbctlr->port_sc1, STS); 326 } 327 #else 328 /* Set to Host mode (if applicable) after Controller Reset was done */ 329 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 330 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 331 /* 332 * Select PHY interface after setting host mode. 333 * For device mode, the ordering requirement is not an issue, since 334 * only the first USB controller supports device mode, and that USB 335 * controller can only talk to a UTMI PHY, so the PHY selection is 336 * already made at reset time, so this write is a no-op. 337 */ 338 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 339 pts << PTS_SHIFT); 340 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 341 #endif 342 } 343 344 /* set up the UTMI USB controller with the parameters provided */ 345 static int init_utmi_usb_controller(struct fdt_usb *config, 346 enum usb_init_type init) 347 { 348 struct fdt_usb_controller *controller; 349 u32 b_sess_valid_mask, val; 350 int loop_count; 351 const unsigned *timing; 352 struct usb_ctlr *usbctlr = config->reg; 353 struct clk_rst_ctlr *clkrst; 354 struct usb_ctlr *usb1ctlr; 355 356 clock_enable(config->periph_id); 357 358 /* Reset the usb controller */ 359 usbf_reset_controller(config, usbctlr); 360 361 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 362 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 363 364 /* Follow the crystal clock disable by >100ns delay */ 365 udelay(1); 366 367 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 368 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 369 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 370 371 /* 372 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 373 * mux must be switched to actually use a_sess_vld threshold. 374 */ 375 if (config->dr_mode == DR_MODE_OTG && 376 dm_gpio_is_valid(&config->vbus_gpio)) 377 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 378 VBUS_SENSE_CTL_MASK, 379 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 380 381 controller = &fdt_usb_controllers[config->type]; 382 debug("controller=%p, type=%d\n", controller, config->type); 383 384 /* 385 * PLL Delay CONFIGURATION settings. The following parameters control 386 * the bring up of the plls. 387 */ 388 timing = get_pll_timing(controller); 389 390 if (!controller->has_hostpc) { 391 val = readl(&usbctlr->utmip_misc_cfg1); 392 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 393 timing[PARAM_STABLE_COUNT] << 394 UTMIP_PLLU_STABLE_COUNT_SHIFT); 395 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 396 timing[PARAM_ACTIVE_DELAY_COUNT] << 397 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 398 writel(val, &usbctlr->utmip_misc_cfg1); 399 400 /* Set PLL enable delay count and crystal frequency count */ 401 val = readl(&usbctlr->utmip_pll_cfg1); 402 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 403 timing[PARAM_ENABLE_DELAY_COUNT] << 404 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 405 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 406 timing[PARAM_XTAL_FREQ_COUNT] << 407 UTMIP_XTAL_FREQ_COUNT_SHIFT); 408 writel(val, &usbctlr->utmip_pll_cfg1); 409 } else { 410 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 411 412 val = readl(&clkrst->crc_utmip_pll_cfg2); 413 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 414 timing[PARAM_STABLE_COUNT] << 415 UTMIP_PLLU_STABLE_COUNT_SHIFT); 416 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 417 timing[PARAM_ACTIVE_DELAY_COUNT] << 418 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 419 writel(val, &clkrst->crc_utmip_pll_cfg2); 420 421 /* Set PLL enable delay count and crystal frequency count */ 422 val = readl(&clkrst->crc_utmip_pll_cfg1); 423 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 424 timing[PARAM_ENABLE_DELAY_COUNT] << 425 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 426 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 427 timing[PARAM_XTAL_FREQ_COUNT] << 428 UTMIP_XTAL_FREQ_COUNT_SHIFT); 429 writel(val, &clkrst->crc_utmip_pll_cfg1); 430 431 /* Disable Power Down state for PLL */ 432 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 433 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 434 PLL_ACTIVE_POWERDOWN); 435 436 /* Recommended PHY settings for EYE diagram */ 437 val = readl(&usbctlr->utmip_xcvr_cfg0); 438 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 439 0x4 << UTMIP_XCVR_SETUP_SHIFT); 440 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 441 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 442 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 443 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 444 writel(val, &usbctlr->utmip_xcvr_cfg0); 445 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 446 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 447 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 448 449 /* Some registers can be controlled from USB1 only. */ 450 if (config->periph_id != PERIPH_ID_USBD) { 451 clock_enable(PERIPH_ID_USBD); 452 /* Disable Reset if in Reset state */ 453 reset_set_enable(PERIPH_ID_USBD, 0); 454 } 455 usb1ctlr = (struct usb_ctlr *) 456 ((unsigned long)config->reg & USB1_ADDR_MASK); 457 val = readl(&usb1ctlr->utmip_bias_cfg0); 458 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 459 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 460 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 461 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 462 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 463 writel(val, &usb1ctlr->utmip_bias_cfg0); 464 465 /* Miscellaneous setting mentioned in Programming Guide */ 466 clrbits_le32(&usbctlr->utmip_misc_cfg0, 467 UTMIP_SUSPEND_EXIT_ON_EDGE); 468 } 469 470 /* Setting the tracking length time */ 471 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 472 UTMIP_BIAS_PDTRK_COUNT_MASK, 473 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 474 475 /* Program debounce time for VBUS to become valid */ 476 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 477 UTMIP_DEBOUNCE_CFG0_MASK, 478 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 479 480 if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) { 481 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 482 UTMIP_DEBOUNCE_CFG0_MASK, 483 (timing[PARAM_DEBOUNCE_A_TIME] >> 1) 484 << UTMIP_DEBOUNCE_CFG0_SHIFT); 485 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 486 UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK, 487 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT); 488 } 489 490 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 491 492 /* Disable battery charge enabling bit */ 493 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 494 495 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 496 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 497 498 /* 499 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 500 * Setting these fields, together with default values of the 501 * other fields, results in programming the registers below as 502 * follows: 503 * UTMIP_HSRX_CFG0 = 0x9168c000 504 * UTMIP_HSRX_CFG1 = 0x13 505 */ 506 507 /* Set PLL enable delay count and Crystal frequency count */ 508 val = readl(&usbctlr->utmip_hsrx_cfg0); 509 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 510 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 511 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 512 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 513 writel(val, &usbctlr->utmip_hsrx_cfg0); 514 515 /* Configure the UTMIP_HS_SYNC_START_DLY */ 516 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 517 UTMIP_HS_SYNC_START_DLY_MASK, 518 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 519 520 /* Preceed the crystal clock disable by >100ns delay. */ 521 udelay(1); 522 523 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 524 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 525 526 if (controller->has_hostpc) { 527 if (config->periph_id == PERIPH_ID_USBD) 528 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 529 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 530 if (config->periph_id == PERIPH_ID_USB2) 531 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 532 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 533 if (config->periph_id == PERIPH_ID_USB3) 534 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 535 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 536 } 537 /* Finished the per-controller init. */ 538 539 /* De-assert UTMIP_RESET to bring out of reset. */ 540 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 541 542 /* Wait for the phy clock to become valid in 100 ms */ 543 for (loop_count = 100000; loop_count != 0; loop_count--) { 544 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 545 break; 546 udelay(1); 547 } 548 if (!loop_count) 549 return -ETIMEDOUT; 550 551 /* Disable ICUSB FS/LS transceiver */ 552 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 553 554 /* Select UTMI parallel interface */ 555 init_phy_mux(config, PTS_UTMI, init); 556 557 /* Deassert power down state */ 558 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 559 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 560 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 561 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 562 563 if (controller->has_hostpc) { 564 /* 565 * BIAS Pad Power Down is common among all 3 USB 566 * controllers and can be controlled from USB1 only. 567 */ 568 usb1ctlr = (struct usb_ctlr *) 569 ((unsigned long)config->reg & USB1_ADDR_MASK); 570 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 571 udelay(25); 572 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 573 UTMIP_FORCE_PDTRK_POWERDOWN); 574 } 575 return 0; 576 } 577 578 #ifdef CONFIG_USB_ULPI 579 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 580 #ifndef CONFIG_ULPI_REF_CLK 581 #define CONFIG_ULPI_REF_CLK 24000000 582 #endif 583 584 /* set up the ULPI USB controller with the parameters provided */ 585 static int init_ulpi_usb_controller(struct fdt_usb *config, 586 enum usb_init_type init) 587 { 588 u32 val; 589 int loop_count; 590 struct ulpi_viewport ulpi_vp; 591 struct usb_ctlr *usbctlr = config->reg; 592 int ret; 593 594 /* set up ULPI reference clock on pllp_out4 */ 595 clock_enable(PERIPH_ID_DEV2_OUT); 596 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 597 598 /* reset ULPI phy */ 599 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 600 /* 601 * This GPIO is typically active-low, and marked as such in 602 * device tree. dm_gpio_set_value() takes this into account 603 * and inverts the value we pass here if required. In other 604 * words, this first call logically asserts the reset signal, 605 * which typically results in driving the physical GPIO low, 606 * and the second call logically de-asserts the reset signal, 607 * which typically results in driver the GPIO high. 608 */ 609 dm_gpio_set_value(&config->phy_reset_gpio, 1); 610 mdelay(5); 611 dm_gpio_set_value(&config->phy_reset_gpio, 0); 612 } 613 614 /* Reset the usb controller */ 615 clock_enable(config->periph_id); 616 usbf_reset_controller(config, usbctlr); 617 618 /* enable pinmux bypass */ 619 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 620 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 621 622 /* Select ULPI parallel interface */ 623 init_phy_mux(config, PTS_ULPI, init); 624 625 /* enable ULPI transceiver */ 626 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 627 628 /* configure ULPI transceiver timings */ 629 val = 0; 630 writel(val, &usbctlr->ulpi_timing_ctrl_1); 631 632 val |= ULPI_DATA_TRIMMER_SEL(4); 633 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 634 val |= ULPI_DIR_TRIMMER_SEL(4); 635 writel(val, &usbctlr->ulpi_timing_ctrl_1); 636 udelay(10); 637 638 val |= ULPI_DATA_TRIMMER_LOAD; 639 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 640 val |= ULPI_DIR_TRIMMER_LOAD; 641 writel(val, &usbctlr->ulpi_timing_ctrl_1); 642 643 /* set up phy for host operation with external vbus supply */ 644 ulpi_vp.port_num = 0; 645 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 646 647 ret = ulpi_init(&ulpi_vp); 648 if (ret) { 649 printf("Tegra ULPI viewport init failed\n"); 650 return ret; 651 } 652 653 ulpi_set_vbus(&ulpi_vp, 1, 1); 654 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 655 656 /* enable wakeup events */ 657 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 658 659 /* Enable and wait for the phy clock to become valid in 100 ms */ 660 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 661 for (loop_count = 100000; loop_count != 0; loop_count--) { 662 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 663 break; 664 udelay(1); 665 } 666 if (!loop_count) 667 return -ETIMEDOUT; 668 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 669 670 return 0; 671 } 672 #else 673 static int init_ulpi_usb_controller(struct fdt_usb *config, 674 enum usb_init_type init) 675 { 676 printf("No code to set up ULPI controller, please enable" 677 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 678 return -ENOSYS; 679 } 680 #endif 681 682 static void config_clock(const u32 timing[]) 683 { 684 debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n", 685 __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], 686 timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); 687 688 clock_start_pll(CLOCK_ID_USB, 689 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 690 timing[PARAM_CPCON], timing[PARAM_LFCON]); 691 } 692 693 static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config) 694 { 695 const char *phy, *mode; 696 697 config->reg = (struct usb_ctlr *)dev_read_addr(dev); 698 debug("reg=%p\n", config->reg); 699 mode = dev_read_string(dev, "dr_mode"); 700 if (mode) { 701 if (0 == strcmp(mode, "host")) 702 config->dr_mode = DR_MODE_HOST; 703 else if (0 == strcmp(mode, "peripheral")) 704 config->dr_mode = DR_MODE_DEVICE; 705 else if (0 == strcmp(mode, "otg")) 706 config->dr_mode = DR_MODE_OTG; 707 else { 708 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 709 mode); 710 return -EINVAL; 711 } 712 } else { 713 config->dr_mode = DR_MODE_HOST; 714 } 715 716 phy = dev_read_string(dev, "phy_type"); 717 config->utmi = phy && 0 == strcmp("utmi", phy); 718 config->ulpi = phy && 0 == strcmp("ulpi", phy); 719 config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode"); 720 config->periph_id = clock_decode_periph_id(dev); 721 if (config->periph_id == PERIPH_ID_NONE) { 722 debug("%s: Missing/invalid peripheral ID\n", __func__); 723 return -EINVAL; 724 } 725 gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio, 726 GPIOD_IS_OUT); 727 gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0, 728 &config->phy_reset_gpio, GPIOD_IS_OUT); 729 debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n", 730 config->has_legacy_mode, config->utmi, config->ulpi, 731 config->periph_id, gpio_get_number(&config->vbus_gpio), 732 gpio_get_number(&config->phy_reset_gpio), config->dr_mode, 733 config->reg); 734 735 return 0; 736 } 737 738 int usb_common_init(struct fdt_usb *config, enum usb_init_type init) 739 { 740 int ret = 0; 741 742 switch (init) { 743 case USB_INIT_HOST: 744 switch (config->dr_mode) { 745 case DR_MODE_HOST: 746 case DR_MODE_OTG: 747 break; 748 default: 749 printf("tegrausb: Invalid dr_mode %d for host mode\n", 750 config->dr_mode); 751 return -1; 752 } 753 break; 754 case USB_INIT_DEVICE: 755 if (config->periph_id != PERIPH_ID_USBD) { 756 printf("tegrausb: Device mode only supported on first USB controller\n"); 757 return -1; 758 } 759 if (!config->utmi) { 760 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 761 return -1; 762 } 763 switch (config->dr_mode) { 764 case DR_MODE_DEVICE: 765 case DR_MODE_OTG: 766 break; 767 default: 768 printf("tegrausb: Invalid dr_mode %d for device mode\n", 769 config->dr_mode); 770 return -1; 771 } 772 break; 773 default: 774 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 775 return -1; 776 } 777 778 debug("%d, %d\n", config->utmi, config->ulpi); 779 if (config->utmi) 780 ret = init_utmi_usb_controller(config, init); 781 else if (config->ulpi) 782 ret = init_ulpi_usb_controller(config, init); 783 if (ret) 784 return ret; 785 786 set_up_vbus(config, init); 787 788 config->init_type = init; 789 790 return 0; 791 } 792 793 void usb_common_uninit(struct fdt_usb *priv) 794 { 795 struct usb_ctlr *usbctlr; 796 797 usbctlr = priv->reg; 798 799 /* Stop controller */ 800 writel(0, &usbctlr->usb_cmd); 801 udelay(1000); 802 803 /* Initiate controller reset */ 804 writel(2, &usbctlr->usb_cmd); 805 udelay(1000); 806 } 807 808 static const struct ehci_ops tegra_ehci_ops = { 809 .set_usb_mode = tegra_ehci_set_usbmode, 810 .get_port_speed = tegra_ehci_get_port_speed, 811 .powerup_fixup = tegra_ehci_powerup_fixup, 812 }; 813 814 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 815 { 816 struct fdt_usb *priv = dev_get_priv(dev); 817 int ret; 818 819 ret = fdt_decode_usb(dev, priv); 820 if (ret) 821 return ret; 822 823 priv->type = dev_get_driver_data(dev); 824 825 return 0; 826 } 827 828 static int ehci_usb_probe(struct udevice *dev) 829 { 830 struct usb_platdata *plat = dev_get_platdata(dev); 831 struct fdt_usb *priv = dev_get_priv(dev); 832 struct ehci_hccr *hccr; 833 struct ehci_hcor *hcor; 834 static bool clk_done; 835 int ret; 836 837 ret = usb_common_init(priv, plat->init_type); 838 if (ret) 839 return ret; 840 hccr = (struct ehci_hccr *)&priv->reg->cap_length; 841 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; 842 if (!clk_done) { 843 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); 844 clk_done = true; 845 } 846 847 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, 848 plat->init_type); 849 } 850 851 static const struct udevice_id ehci_usb_ids[] = { 852 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, 853 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, 854 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, 855 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 }, 856 { } 857 }; 858 859 U_BOOT_DRIVER(usb_ehci) = { 860 .name = "ehci_tegra", 861 .id = UCLASS_USB, 862 .of_match = ehci_usb_ids, 863 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 864 .probe = ehci_usb_probe, 865 .remove = ehci_deregister, 866 .ops = &ehci_usb_ops, 867 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 868 .priv_auto_alloc_size = sizeof(struct fdt_usb), 869 .flags = DM_FLAG_ALLOC_PRIV_DMA, 870 }; 871