1 /* 2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dt-bindings/memory/rk3368-dmc.h> 11 #include <dt-structs.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cru_rk3368.h> 18 #include <asm/arch/grf_rk3368.h> 19 #include <asm/arch/ddr_rk3368.h> 20 #include <asm/arch/sdram.h> 21 #include <asm/arch/sdram_common.h> 22 23 struct dram_info { 24 struct ram_info info; 25 struct clk ddr_clk; 26 struct rk3368_cru *cru; 27 struct rk3368_grf *grf; 28 struct rk3368_ddr_pctl *pctl; 29 struct rk3368_ddrphy *phy; 30 struct rk3368_pmu_grf *pmugrf; 31 struct rk3368_msch *msch; 32 }; 33 34 struct rk3368_sdram_params { 35 #if CONFIG_IS_ENABLED(OF_PLATDATA) 36 struct dtd_rockchip_rk3368_dmc of_plat; 37 #endif 38 struct rk3288_sdram_pctl_timing pctl_timing; 39 u32 trefi_mem_ddr3; 40 struct rk3288_sdram_channel chan; 41 struct regmap *map; 42 u32 ddr_freq; 43 u32 memory_schedule; 44 u32 ddr_speed_bin; 45 u32 tfaw_mult; 46 }; 47 48 /* PTCL bits */ 49 enum { 50 /* PCTL_DFISTCFG0 */ 51 DFI_INIT_START = BIT(0), 52 DFI_DATA_BYTE_DISABLE_EN = BIT(2), 53 54 /* PCTL_DFISTCFG1 */ 55 DFI_DRAM_CLK_SR_EN = BIT(0), 56 DFI_DRAM_CLK_DPD_EN = BIT(1), 57 ODT_LEN_BL8_W_SHIFT = 16, 58 59 /* PCTL_DFISTCFG2 */ 60 DFI_PARITY_INTR_EN = BIT(0), 61 DFI_PARITY_EN = BIT(1), 62 63 /* PCTL_DFILPCFG0 */ 64 TLP_RESP_TIME_SHIFT = 16, 65 LP_SR_EN = BIT(8), 66 LP_PD_EN = BIT(0), 67 68 /* PCTL_DFIODTCFG */ 69 RANK0_ODT_WRITE_SEL = BIT(3), 70 RANK1_ODT_WRITE_SEL = BIT(11), 71 72 /* PCTL_SCFG */ 73 HW_LOW_POWER_EN = BIT(0), 74 75 /* PCTL_MCMD */ 76 START_CMD = BIT(31), 77 MCMD_RANK0 = BIT(20), 78 MCMD_RANK1 = BIT(21), 79 DESELECT_CMD = 0, 80 PREA_CMD, 81 REF_CMD, 82 MRS_CMD, 83 ZQCS_CMD, 84 ZQCL_CMD, 85 RSTL_CMD, 86 MRR_CMD = 8, 87 DPDE_CMD, 88 89 /* PCTL_POWCTL */ 90 POWER_UP_START = BIT(0), 91 92 /* PCTL_POWSTAT */ 93 POWER_UP_DONE = BIT(0), 94 95 /* PCTL_SCTL */ 96 INIT_STATE = 0, 97 CFG_STATE, 98 GO_STATE, 99 SLEEP_STATE, 100 WAKEUP_STATE, 101 102 /* PCTL_STAT */ 103 LP_TRIG_SHIFT = 4, 104 LP_TRIG_MASK = 7, 105 PCTL_STAT_MSK = 7, 106 INIT_MEM = 0, 107 CONFIG, 108 CONFIG_REQ, 109 ACCESS, 110 ACCESS_REQ, 111 LOW_POWER, 112 LOW_POWER_ENTRY_REQ, 113 LOW_POWER_EXIT_REQ, 114 115 /* PCTL_MCFG */ 116 DDR2_DDR3_BL_8 = BIT(0), 117 DDR3_EN = BIT(5), 118 TFAW_TRRD_MULT4 = (0 << 18), 119 TFAW_TRRD_MULT5 = (1 << 18), 120 TFAW_TRRD_MULT6 = (2 << 18), 121 }; 122 123 #define DDR3_MR0_WR(n) \ 124 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) 125 #define DDR3_MR0_CL(n) \ 126 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) 127 #define DDR3_MR0_BL8 \ 128 (0 << 0) 129 #define DDR3_MR0_DLL_RESET \ 130 (1 << 8) 131 #define DDR3_MR1_RTT120OHM \ 132 ((0 << 9) | (1 << 6) | (0 << 2)) 133 #define DDR3_MR2_TWL(n) \ 134 (((n - 5) & 0x7) << 3) 135 136 137 #ifdef CONFIG_TPL_BUILD 138 139 static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable) 140 { 141 if (enable) 142 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); 143 else 144 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); 145 } 146 147 static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode) 148 { 149 if (ddr3_mode) 150 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); 151 else 152 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); 153 } 154 155 static void ddrphy_config(struct rk3368_ddrphy *phy, 156 u32 tcl, u32 tal, u32 tcwl) 157 { 158 int i; 159 160 /* Set to DDR3 mode */ 161 clrsetbits_le32(&phy->reg[1], 0x3, 0x0); 162 163 /* DDRPHY_REGB: CL, AL */ 164 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); 165 /* DDRPHY_REGC: CWL */ 166 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); 167 168 /* Update drive-strength */ 169 writel(0xcc, &phy->reg[0x11]); 170 writel(0xaa, &phy->reg[0x16]); 171 /* 172 * Update NRCOMP/PRCOMP for all 4 channels (for details of all 173 * affected registers refer to the documentation of DDRPHY_REG20 174 * and DDRPHY_REG21 in the RK3368 TRM. 175 */ 176 for (i = 0; i < 4; ++i) { 177 writel(0xcc, &phy->reg[0x20 + i * 0x10]); 178 writel(0x44, &phy->reg[0x21 + i * 0x10]); 179 } 180 181 /* Enable write-leveling calibration bypass */ 182 setbits_le32(&phy->reg[2], BIT(3)); 183 } 184 185 static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 186 { 187 int i; 188 189 for (i = 0; i < n / sizeof(u32); i++) 190 writel(*src++, dest++); 191 } 192 193 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) 194 { 195 u32 mcmd = START_CMD | cmd | rank; 196 197 debug("%s: writing %x to MCMD\n", __func__, mcmd); 198 writel(mcmd, &pctl->mcmd); 199 while (readl(&pctl->mcmd) & START_CMD) 200 /* spin */; 201 } 202 203 static void send_mrs(struct rk3368_ddr_pctl *pctl, 204 u32 rank, u32 mr_num, u32 mr_data) 205 { 206 u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4); 207 208 debug("%s: writing %x to MCMD\n", __func__, mcmd); 209 writel(mcmd, &pctl->mcmd); 210 while (readl(&pctl->mcmd) & START_CMD) 211 /* spin */; 212 } 213 214 static int memory_init(struct rk3368_ddr_pctl *pctl, 215 struct rk3368_sdram_params *params) 216 { 217 u32 mr[4]; 218 const ulong timeout_ms = 500; 219 ulong tmp; 220 221 /* 222 * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and 223 * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register 224 * of PCTL. 225 */ 226 writel(POWER_UP_START, &pctl->powctl); 227 228 tmp = get_timer(0); 229 do { 230 if (get_timer(tmp) > timeout_ms) { 231 pr_err("%s: POWER_UP_START did not complete in %ld ms\n", 232 __func__, timeout_ms); 233 return -ETIME; 234 } 235 } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); 236 237 /* Configure MR0 through MR3 */ 238 mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) | 239 DDR3_MR0_CL(params->pctl_timing.tcl) | 240 DDR3_MR0_DLL_RESET; 241 mr[1] = DDR3_MR1_RTT120OHM; 242 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); 243 mr[3] = 0; 244 245 /* 246 * Also see RK3368 Technical Reference Manual: 247 * "16.6.2 Initialization (DDR3 Initialization Sequence)" 248 */ 249 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD); 250 udelay(1); 251 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); 252 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]); 253 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]); 254 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]); 255 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]); 256 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD); 257 258 return 0; 259 } 260 261 static void move_to_config_state(struct rk3368_ddr_pctl *pctl) 262 { 263 /* 264 * Also see RK3368 Technical Reference Manual: 265 * "16.6.1 State transition of PCTL (Moving to Config State)" 266 */ 267 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; 268 269 switch (state) { 270 case LOW_POWER: 271 writel(WAKEUP_STATE, &pctl->sctl); 272 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 273 /* spin */; 274 275 /* fall-through */ 276 case ACCESS: 277 case INIT_MEM: 278 writel(CFG_STATE, &pctl->sctl); 279 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 280 /* spin */; 281 break; 282 283 case CONFIG: 284 return; 285 286 default: 287 break; 288 } 289 } 290 291 static void move_to_access_state(struct rk3368_ddr_pctl *pctl) 292 { 293 /* 294 * Also see RK3368 Technical Reference Manual: 295 * "16.6.1 State transition of PCTL (Moving to Access State)" 296 */ 297 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; 298 299 switch (state) { 300 case LOW_POWER: 301 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & 302 LP_TRIG_MASK) == 1) 303 return; 304 305 writel(WAKEUP_STATE, &pctl->sctl); 306 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 307 /* spin */; 308 309 /* fall-through */ 310 case INIT_MEM: 311 writel(CFG_STATE, &pctl->sctl); 312 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 313 /* spin */; 314 315 /* fall-through */ 316 case CONFIG: 317 writel(GO_STATE, &pctl->sctl); 318 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) 319 /* spin */; 320 break; 321 322 case ACCESS: 323 return; 324 325 default: 326 break; 327 } 328 } 329 330 static void ddrctl_reset(struct rk3368_cru *cru) 331 { 332 const u32 ctl_reset = BIT(3) | BIT(2); 333 const u32 phy_reset = BIT(1) | BIT(0); 334 335 /* 336 * The PHY reset should be released before the PCTL reset. 337 * 338 * Note that the following sequence (including the number of 339 * us to delay between releasing the PHY and PCTL reset) has 340 * been adapted per feedback received from Rockchips, so do 341 * not try to optimise. 342 */ 343 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); 344 udelay(1); 345 rk_clrreg(&cru->softrst_con[10], phy_reset); 346 udelay(5); 347 rk_clrreg(&cru->softrst_con[10], ctl_reset); 348 } 349 350 static void ddrphy_reset(struct rk3368_ddrphy *ddrphy) 351 { 352 /* 353 * The analog part of the PHY should be release at least 1000 354 * DRAM cycles before the digital part of the PHY (waiting for 355 * 5us will ensure this for a DRAM clock as low as 200MHz). 356 */ 357 clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2)); 358 udelay(1); 359 setbits_le32(&ddrphy->reg[0], BIT(2)); 360 udelay(5); 361 setbits_le32(&ddrphy->reg[0], BIT(3)); 362 } 363 364 static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq) 365 { 366 u32 dqs_dll_delay; 367 368 setbits_le32(&ddrphy->reg[0x13], BIT(4)); 369 clrbits_le32(&ddrphy->reg[0x14], BIT(3)); 370 371 setbits_le32(&ddrphy->reg[0x26], BIT(4)); 372 clrbits_le32(&ddrphy->reg[0x27], BIT(3)); 373 374 setbits_le32(&ddrphy->reg[0x36], BIT(4)); 375 clrbits_le32(&ddrphy->reg[0x37], BIT(3)); 376 377 setbits_le32(&ddrphy->reg[0x46], BIT(4)); 378 clrbits_le32(&ddrphy->reg[0x47], BIT(3)); 379 380 setbits_le32(&ddrphy->reg[0x56], BIT(4)); 381 clrbits_le32(&ddrphy->reg[0x57], BIT(3)); 382 383 if (freq <= 400000000) 384 setbits_le32(&ddrphy->reg[0xa4], 0x1f); 385 else 386 clrbits_le32(&ddrphy->reg[0xa4], 0x1f); 387 388 if (freq < 681000000) 389 dqs_dll_delay = 3; /* 67.5 degree delay */ 390 else 391 dqs_dll_delay = 2; /* 45 degree delay */ 392 393 writel(dqs_dll_delay, &ddrphy->reg[0x28]); 394 writel(dqs_dll_delay, &ddrphy->reg[0x38]); 395 writel(dqs_dll_delay, &ddrphy->reg[0x48]); 396 writel(dqs_dll_delay, &ddrphy->reg[0x58]); 397 } 398 399 static int dfi_cfg(struct rk3368_ddr_pctl *pctl) 400 { 401 const ulong timeout_ms = 200; 402 ulong tmp; 403 404 writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); 405 406 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, 407 &pctl->dfistcfg1); 408 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 409 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 410 &pctl->dfilpcfg0); 411 412 writel(1, &pctl->dfitphyupdtype0); 413 414 writel(0x1f, &pctl->dfitphyrdlat); 415 writel(0, &pctl->dfitphywrdata); 416 writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */ 417 418 setbits_le32(&pctl->dfistcfg0, DFI_INIT_START); 419 420 tmp = get_timer(0); 421 do { 422 if (get_timer(tmp) > timeout_ms) { 423 pr_err("%s: DFI init did not complete within %ld ms\n", 424 __func__, timeout_ms); 425 return -ETIME; 426 } 427 } while ((readl(&pctl->dfiststat0) & 1) == 0); 428 429 return 0; 430 } 431 432 static inline u32 ps_to_tCK(const u32 ps, const ulong freq) 433 { 434 const ulong MHz = 1000000; 435 return DIV_ROUND_UP(ps * freq, 1000000 * MHz); 436 } 437 438 static inline u32 ns_to_tCK(const u32 ns, const ulong freq) 439 { 440 return ps_to_tCK(ns * 1000, freq); 441 } 442 443 static inline u32 tCK_to_ps(const ulong tCK, const ulong freq) 444 { 445 const ulong MHz = 1000000; 446 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq); 447 } 448 449 static int pctl_calc_timings(struct rk3368_sdram_params *params, 450 ulong freq) 451 { 452 struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; 453 const ulong MHz = 1000000; 454 u32 tccd; 455 u32 tfaw_as_ps; 456 457 if (params->ddr_speed_bin != DDR3_1600K) { 458 pr_err("%s: unimplemented DDR3 speed bin %d\n", 459 __func__, params->ddr_speed_bin); 460 return -1; 461 } 462 463 /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ 464 pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz); 465 pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz); 466 467 pctl_timing->tinit = 200; /* 200 usec */ 468 pctl_timing->trsth = 500; /* 500 usec */ 469 pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */ 470 params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq); 471 472 if (freq <= (400 * MHz)) { 473 pctl_timing->tcl = 6; 474 pctl_timing->tcwl = 10; 475 } else if (freq <= (533 * MHz)) { 476 pctl_timing->tcl = 8; 477 pctl_timing->tcwl = 6; 478 } else if (freq <= (666 * MHz)) { 479 pctl_timing->tcl = 10; 480 pctl_timing->tcwl = 7; 481 } else { 482 pctl_timing->tcl = 11; 483 pctl_timing->tcwl = 8; 484 } 485 486 pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */ 487 pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */ 488 pctl_timing->trp = max(4u, ps_to_tCK(13750, freq)); 489 /* 490 * JESD-79: 491 * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL 492 */ 493 tccd = 4; 494 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; 495 pctl_timing->tal = 0; 496 pctl_timing->tras = ps_to_tCK(35000, freq); 497 pctl_timing->trc = ps_to_tCK(48750, freq); 498 pctl_timing->trcd = ps_to_tCK(13750, freq); 499 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); 500 pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq)); 501 pctl_timing->twr = ps_to_tCK(15000, freq); 502 /* The DDR3 mode-register does only support even values for tWR > 8. */ 503 if (pctl_timing->twr > 8) 504 pctl_timing->twr = (pctl_timing->twr + 1) & ~1; 505 pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq)); 506 pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */ 507 pctl_timing->txp = max(3u, ps_to_tCK(6000, freq)); 508 pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq)); 509 pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq)); 510 pctl_timing->tzqcsi = 10000; /* as used by Rockchip */ 511 pctl_timing->tdqs = 1; /* fixed for DDR3 */ 512 pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq)); 513 pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq)); 514 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); 515 pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq)); 516 pctl_timing->trstl = ns_to_tCK(100, freq); 517 pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */ 518 pctl_timing->tmrr = 0; 519 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ 520 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */ 521 522 523 /* 524 * The controller can represent tFAW as 4x, 5x or 6x tRRD only. 525 * We want to use the smallest multiplier that satisfies the tFAW 526 * requirements of the given speed-bin. If necessary, we stretch out 527 * tRRD to allow us to operate on a 6x multiplier for tFAW. 528 */ 529 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */ 530 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { 531 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ 532 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); 533 params->tfaw_mult = TFAW_TRRD_MULT6; 534 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { 535 params->tfaw_mult = TFAW_TRRD_MULT6; 536 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { 537 params->tfaw_mult = TFAW_TRRD_MULT5; 538 } else { 539 params->tfaw_mult = TFAW_TRRD_MULT4; 540 } 541 542 return 0; 543 } 544 545 static void pctl_cfg(struct rk3368_ddr_pctl *pctl, 546 struct rk3368_sdram_params *params, 547 struct rk3368_grf *grf) 548 { 549 /* Configure PCTL timing registers */ 550 params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */ 551 copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, 552 sizeof(params->pctl_timing)); 553 writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); 554 555 /* Set up ODT write selector and ODT write length */ 556 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg); 557 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 558 559 /* Set up the CL/CWL-dependent timings of DFI */ 560 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); 561 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); 562 563 /* DDR3 */ 564 writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg); 565 writel(0x001c0004, &grf->ddrc0_con0); 566 567 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); 568 } 569 570 static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl, 571 struct rk3368_ddrphy *ddrphy) 572 { 573 const u32 trefi = readl(&pctl->trefi); 574 const ulong timeout_ms = 500; 575 ulong tmp; 576 577 /* disable auto-refresh */ 578 writel(0 | BIT(31), &pctl->trefi); 579 580 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); 581 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21); 582 583 tmp = get_timer(0); 584 do { 585 if (get_timer(tmp) > timeout_ms) { 586 pr_err("%s: did not complete within %ld ms\n", 587 __func__, timeout_ms); 588 return -ETIME; 589 } 590 } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf); 591 592 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); 593 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); 594 /* resume auto-refresh */ 595 writel(trefi | BIT(31), &pctl->trefi); 596 597 return 0; 598 } 599 600 static int sdram_col_row_detect(struct udevice *dev) 601 { 602 struct dram_info *priv = dev_get_priv(dev); 603 struct rk3368_sdram_params *params = dev_get_platdata(dev); 604 struct rk3368_ddr_pctl *pctl = priv->pctl; 605 struct rk3368_msch *msch = priv->msch; 606 const u32 test_pattern = 0x5aa5f00f; 607 int row, col; 608 uintptr_t addr; 609 610 move_to_config_state(pctl); 611 writel(6, &msch->ddrconf); 612 move_to_access_state(pctl); 613 614 /* Detect col */ 615 for (col = 11; col >= 9; col--) { 616 writel(0, CONFIG_SYS_SDRAM_BASE); 617 addr = CONFIG_SYS_SDRAM_BASE + 618 (1 << (col + params->chan.bw - 1)); 619 writel(test_pattern, addr); 620 if ((readl(addr) == test_pattern) && 621 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 622 break; 623 } 624 625 if (col == 8) { 626 pr_err("%s: col detect error\n", __func__); 627 return -EINVAL; 628 } 629 630 move_to_config_state(pctl); 631 writel(15, &msch->ddrconf); 632 move_to_access_state(pctl); 633 634 /* Detect row*/ 635 for (row = 16; row >= 12; row--) { 636 writel(0, CONFIG_SYS_SDRAM_BASE); 637 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); 638 writel(test_pattern, addr); 639 if ((readl(addr) == test_pattern) && 640 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 641 break; 642 } 643 644 if (row == 11) { 645 pr_err("%s: row detect error\n", __func__); 646 return -EINVAL; 647 } 648 649 /* Record results */ 650 debug("%s: col %d, row %d\n", __func__, col, row); 651 params->chan.col = col; 652 params->chan.cs0_row = row; 653 params->chan.cs1_row = row; 654 params->chan.row_3_4 = 0; 655 656 return 0; 657 } 658 659 static int msch_niu_config(struct rk3368_msch *msch, 660 struct rk3368_sdram_params *params) 661 { 662 int i; 663 const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1); 664 const u8 rows = params->chan.cs0_row; 665 666 /* 667 * The DDR address-translation table always assumes a 32bit 668 * bus and the comparison below takes care of adjusting for 669 * a 16bit bus (i.e. one column-address is consumed). 670 */ 671 const struct { 672 u8 rows; 673 u8 columns; 674 u8 type; 675 } ddrconf_table[] = { 676 /* 677 * C-B-R-D patterns are first. For these we require an 678 * exact match for the columns and rows (as there's 679 * one entry per possible configuration). 680 */ 681 [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD }, 682 [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD }, 683 [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD }, 684 [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD }, 685 [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD }, 686 [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD }, 687 [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD }, 688 [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD }, 689 [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD }, 690 [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD }, 691 [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD }, 692 /* 693 * 11 through 13 are C-R-B-D patterns. These are 694 * matched for an exact number of columns and to 695 * ensure that the hardware uses at least as many rows 696 * as the pattern requires (i.e. we make sure that 697 * there's no gaps up until we hit the device/chip-select; 698 * however, these patterns can accept up to 16 rows, 699 * as the row-address continues right after the CS 700 * switching) 701 */ 702 [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD }, 703 [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD }, 704 [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD }, 705 /* 706 * 14 and 15 are catch-all variants using a C-B-D-R 707 * scheme (i.e. alternating the chip-select every time 708 * C-B overflows) and stuffing the remaining C-bits 709 * into the top. Matching needs to make sure that the 710 * number of columns is either an exact match (i.e. we 711 * can use less the the maximum number of rows) -or- 712 * that the columns exceed what is given in this table 713 * and the rows are an exact match (in which case the 714 * remaining C-bits will be stuffed onto the top after 715 * the device/chip-select switches). 716 */ 717 [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR }, 718 [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR }, 719 }; 720 721 /* 722 * For C-B-R-D, we need an exact match (i.e. both for the number of 723 * columns and rows), while for C-B-D-R, only the the number of 724 * columns needs to match. 725 */ 726 for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) { 727 bool match = false; 728 729 /* If this entry if for a different matcher, then skip it */ 730 if (ddrconf_table[i].type != params->memory_schedule) 731 continue; 732 733 /* 734 * Match according to the rules (exact/inexact/at-least) 735 * documented in the ddrconf_table above. 736 */ 737 switch (params->memory_schedule) { 738 case DMC_MSCH_CBRD: 739 match = (ddrconf_table[i].columns == cols) && 740 (ddrconf_table[i].rows == rows); 741 break; 742 743 case DMC_MSCH_CRBD: 744 match = (ddrconf_table[i].columns == cols) && 745 (ddrconf_table[i].rows <= rows); 746 break; 747 748 case DMC_MSCH_CBDR: 749 match = (ddrconf_table[i].columns == cols) || 750 ((ddrconf_table[i].columns <= cols) && 751 (ddrconf_table[i].rows == rows)); 752 break; 753 754 default: 755 break; 756 } 757 758 if (match) { 759 debug("%s: setting ddrconf 0x%x\n", __func__, i); 760 writel(i, &msch->ddrconf); 761 return 0; 762 } 763 } 764 765 pr_err("%s: ddrconf (NIU config) not found\n", __func__); 766 return -EINVAL; 767 } 768 769 static void dram_all_config(struct udevice *dev) 770 { 771 struct dram_info *priv = dev_get_priv(dev); 772 struct rk3368_pmu_grf *pmugrf = priv->pmugrf; 773 struct rk3368_sdram_params *params = dev_get_platdata(dev); 774 const struct rk3288_sdram_channel *info = ¶ms->chan; 775 u32 sys_reg = 0; 776 const int chan = 0; 777 778 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT; 779 sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT; 780 781 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); 782 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); 783 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); 784 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); 785 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); 786 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); 787 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); 788 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); 789 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); 790 791 writel(sys_reg, &pmugrf->os_reg[2]); 792 } 793 794 static int setup_sdram(struct udevice *dev) 795 { 796 struct dram_info *priv = dev_get_priv(dev); 797 struct rk3368_sdram_params *params = dev_get_platdata(dev); 798 799 struct rk3368_ddr_pctl *pctl = priv->pctl; 800 struct rk3368_ddrphy *ddrphy = priv->phy; 801 struct rk3368_cru *cru = priv->cru; 802 struct rk3368_grf *grf = priv->grf; 803 struct rk3368_msch *msch = priv->msch; 804 805 int ret; 806 807 /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ 808 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); 809 if (ret < 0) { 810 debug("%s: could not set DDR clock: %d\n", __func__, ret); 811 return ret; 812 } 813 814 /* Update the read-latency for the RK3368 */ 815 writel(0x32, &msch->readlatency); 816 817 /* Initialise the DDR PCTL and DDR PHY */ 818 ddrctl_reset(cru); 819 ddrphy_reset(ddrphy); 820 ddrphy_config_delays(ddrphy, params->ddr_freq); 821 dfi_cfg(pctl); 822 /* Configure relative system information of grf_ddrc0_con0 register */ 823 ddr_set_ddr3_mode(grf, true); 824 ddr_set_noc_spr_err_stall(grf, true); 825 /* Calculate timings */ 826 pctl_calc_timings(params, params->ddr_freq); 827 /* Initialise the device timings in protocol controller */ 828 pctl_cfg(pctl, params, grf); 829 /* Configure AL, CL ... information of PHY registers */ 830 ddrphy_config(ddrphy, 831 params->pctl_timing.tcl, 832 params->pctl_timing.tal, 833 params->pctl_timing.tcwl); 834 835 /* Initialize DRAM and configure with mode-register values */ 836 ret = memory_init(pctl, params); 837 if (ret) 838 goto error; 839 840 move_to_config_state(pctl); 841 /* Perform data-training */ 842 ddrphy_data_training(pctl, ddrphy); 843 move_to_access_state(pctl); 844 845 /* TODO(prt): could detect rank in training... */ 846 params->chan.rank = 2; 847 /* TODO(prt): bus width is not auto-detected (yet)... */ 848 params->chan.bw = 2; /* 32bit wide bus */ 849 params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ 850 851 /* DDR3 is always 8 bank */ 852 params->chan.bk = 3; 853 /* Detect col and row number */ 854 ret = sdram_col_row_detect(dev); 855 if (ret) 856 goto error; 857 858 /* Configure NIU DDR configuration */ 859 ret = msch_niu_config(msch, params); 860 if (ret) 861 goto error; 862 863 /* set up OS_REG to communicate w/ next stage and OS */ 864 dram_all_config(dev); 865 866 return 0; 867 868 error: 869 printf("DRAM init failed!\n"); 870 hang(); 871 } 872 #endif 873 874 static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev) 875 { 876 int ret = 0; 877 878 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 879 struct rk3368_sdram_params *plat = dev_get_platdata(dev); 880 881 ret = regmap_init_mem(dev, &plat->map); 882 if (ret) 883 return ret; 884 #endif 885 886 return ret; 887 } 888 889 #if CONFIG_IS_ENABLED(OF_PLATDATA) 890 static int conv_of_platdata(struct udevice *dev) 891 { 892 struct rk3368_sdram_params *plat = dev_get_platdata(dev); 893 struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; 894 895 plat->ddr_freq = of_plat->rockchip_ddr_frequency; 896 plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; 897 plat->memory_schedule = of_plat->rockchip_memory_schedule; 898 899 return 0; 900 } 901 #endif 902 903 static int rk3368_dmc_probe(struct udevice *dev) 904 { 905 #ifdef CONFIG_TPL_BUILD 906 struct rk3368_sdram_params *plat = dev_get_platdata(dev); 907 struct rk3368_ddr_pctl *pctl; 908 struct rk3368_ddrphy *ddrphy; 909 struct rk3368_cru *cru; 910 struct rk3368_grf *grf; 911 struct rk3368_msch *msch; 912 int ret; 913 struct udevice *dev_clk; 914 #endif 915 struct dram_info *priv = dev_get_priv(dev); 916 917 #if CONFIG_IS_ENABLED(OF_PLATDATA) 918 ret = conv_of_platdata(dev); 919 if (ret) 920 return ret; 921 #endif 922 923 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 924 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); 925 926 #ifdef CONFIG_TPL_BUILD 927 pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0]; 928 ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2]; 929 msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); 930 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 931 932 priv->pctl = pctl; 933 priv->phy = ddrphy; 934 priv->msch = msch; 935 priv->grf = grf; 936 937 ret = rockchip_get_clk(&dev_clk); 938 if (ret) 939 return ret; 940 priv->ddr_clk.id = CLK_DDR; 941 ret = clk_request(dev_clk, &priv->ddr_clk); 942 if (ret) 943 return ret; 944 945 cru = rockchip_get_cru(); 946 priv->cru = cru; 947 if (IS_ERR(priv->cru)) 948 return PTR_ERR(priv->cru); 949 950 ret = setup_sdram(dev); 951 if (ret) 952 return ret; 953 #endif 954 955 priv->info.base = 0; 956 priv->info.size = 957 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); 958 959 /* 960 * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff 961 * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is 962 * inaccessible for some IP controller. 963 */ 964 priv->info.size = min(priv->info.size, (size_t)0xfe000000); 965 966 return 0; 967 } 968 969 static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) 970 { 971 struct dram_info *priv = dev_get_priv(dev); 972 973 *info = priv->info; 974 return 0; 975 } 976 977 static struct ram_ops rk3368_dmc_ops = { 978 .get_info = rk3368_dmc_get_info, 979 }; 980 981 982 static const struct udevice_id rk3368_dmc_ids[] = { 983 { .compatible = "rockchip,rk3368-dmc" }, 984 { } 985 }; 986 987 U_BOOT_DRIVER(dmc_rk3368) = { 988 .name = "rockchip_rk3368_dmc", 989 .id = UCLASS_RAM, 990 .of_match = rk3368_dmc_ids, 991 .ops = &rk3368_dmc_ops, 992 .probe = rk3368_dmc_probe, 993 .priv_auto_alloc_size = sizeof(struct dram_info), 994 .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, 995 .probe = rk3368_dmc_probe, 996 .priv_auto_alloc_size = sizeof(struct dram_info), 997 .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params), 998 }; 999