1 /* 2 * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/hardware.h> 12 13 #ifndef CONFIG_ZYNQ_DDRC_INIT 14 void zynq_ddrc_init(void) {} 15 #else 16 /* Control regsiter bitfield definitions */ 17 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC 18 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 19 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1 20 21 /* ECC scrub regsiter definitions */ 22 #define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7 23 #define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4 24 25 void zynq_ddrc_init(void) 26 { 27 u32 width, ecctype; 28 29 width = readl(&ddrc_base->ddrc_ctrl); 30 width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >> 31 ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT; 32 ecctype = (readl(&ddrc_base->ecc_scrub) & 33 ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK); 34 35 /* ECC is enabled when memory is in 16bit mode and it is enabled */ 36 if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && 37 (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { 38 puts("ECC enabled "); 39 /* 40 * Clear the first 1MB because it is not initialized from 41 * first stage bootloader. To get ECC to work all memory has 42 * been initialized by writing any value. 43 */ 44 /* cppcheck-suppress nullPointer */ 45 memset((void *)0, 0, 1 * 1024 * 1024); 46 } else { 47 puts("ECC disabled "); 48 } 49 } 50 #endif 51