1 /* 2 * Copyright 2014-2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_immap.h> 9 #include <fsl_ifc.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/soc.h> 14 #include <asm/io.h> 15 #include <asm/global_data.h> 16 #include <asm/arch-fsl-layerscape/config.h> 17 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 18 #include <fsl_csu.h> 19 #endif 20 #ifdef CONFIG_SYS_FSL_DDR 21 #include <fsl_ddr_sdram.h> 22 #include <fsl_ddr.h> 23 #endif 24 #ifdef CONFIG_CHAIN_OF_TRUST 25 #include <fsl_validate.h> 26 #endif 27 #include <fsl_immap.h> 28 29 bool soc_has_dp_ddr(void) 30 { 31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 32 u32 svr = gur_in32(&gur->svr); 33 34 /* LS2085A, LS2088A, LS2048A has DP_DDR */ 35 if ((SVR_SOC_VER(svr) == SVR_LS2085A) || 36 (SVR_SOC_VER(svr) == SVR_LS2088A) || 37 (SVR_SOC_VER(svr) == SVR_LS2048A)) 38 return true; 39 40 return false; 41 } 42 43 bool soc_has_aiop(void) 44 { 45 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 46 u32 svr = gur_in32(&gur->svr); 47 48 /* LS2085A has AIOP */ 49 if (SVR_SOC_VER(svr) == SVR_LS2085A) 50 return true; 51 52 return false; 53 } 54 55 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) 56 { 57 scfg_clrsetbits32(scfg + offset / 4, 58 0xF << 6, 59 SCFG_USB_TXVREFTUNE << 6); 60 } 61 62 static void erratum_a009008(void) 63 { 64 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 65 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 66 67 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 68 defined(CONFIG_ARCH_LS1012A) 69 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); 70 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 71 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); 72 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); 73 #endif 74 #elif defined(CONFIG_ARCH_LS2080A) 75 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); 76 #endif 77 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ 78 } 79 80 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) 81 { 82 scfg_clrbits32(scfg + offset / 4, 83 SCFG_USB_SQRXTUNE_MASK << 23); 84 } 85 86 static void erratum_a009798(void) 87 { 88 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 89 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 90 91 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 92 defined(CONFIG_ARCH_LS1012A) 93 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); 94 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 95 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); 96 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); 97 #endif 98 #elif defined(CONFIG_ARCH_LS2080A) 99 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); 100 #endif 101 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ 102 } 103 104 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 105 defined(CONFIG_ARCH_LS1012A) 106 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) 107 { 108 scfg_clrsetbits32(scfg + offset / 4, 109 0x7F << 9, 110 SCFG_USB_PCSTXSWINGFULL << 9); 111 } 112 #endif 113 114 static void erratum_a008997(void) 115 { 116 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 117 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 118 defined(CONFIG_ARCH_LS1012A) 119 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 120 121 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); 122 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 123 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); 124 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); 125 #endif 126 #endif 127 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ 128 } 129 130 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 131 defined(CONFIG_ARCH_LS1012A) 132 133 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 134 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 135 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 136 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 137 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 138 139 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 140 141 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ 142 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ 143 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ 144 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ 145 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) 146 147 #endif 148 149 static void erratum_a009007(void) 150 { 151 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ 152 defined(CONFIG_ARCH_LS1012A) 153 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; 154 155 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 156 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) 157 usb_phy = (void __iomem *)SCFG_USB_PHY2; 158 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 159 160 usb_phy = (void __iomem *)SCFG_USB_PHY3; 161 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); 162 #endif 163 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) 164 void __iomem *dcsr = (void __iomem *)DCSR_BASE; 165 166 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); 167 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); 168 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ 169 } 170 171 #if defined(CONFIG_FSL_LSCH3) 172 /* 173 * This erratum requires setting a value to eddrtqcr1 to 174 * optimal the DDR performance. 175 */ 176 static void erratum_a008336(void) 177 { 178 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 179 u32 *eddrtqcr1; 180 181 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR 182 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; 183 if (fsl_ddr_get_version(0) == 0x50200) 184 out_le32(eddrtqcr1, 0x63b30002); 185 #endif 186 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR 187 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; 188 if (fsl_ddr_get_version(0) == 0x50200) 189 out_le32(eddrtqcr1, 0x63b30002); 190 #endif 191 #endif 192 } 193 194 /* 195 * This erratum requires a register write before being Memory 196 * controller 3 being enabled. 197 */ 198 static void erratum_a008514(void) 199 { 200 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 201 u32 *eddrtqcr1; 202 203 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR 204 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; 205 out_le32(eddrtqcr1, 0x63b20002); 206 #endif 207 #endif 208 } 209 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 210 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" 211 212 static unsigned long get_internval_val_mhz(void) 213 { 214 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); 215 /* 216 * interval is the number of platform cycles(MHz) between 217 * wake up events generated by EPU. 218 */ 219 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); 220 221 if (interval) 222 interval_mhz = simple_strtoul(interval, NULL, 10); 223 224 return interval_mhz; 225 } 226 227 void erratum_a009635(void) 228 { 229 u32 val; 230 unsigned long interval_mhz = get_internval_val_mhz(); 231 232 if (!interval_mhz) 233 return; 234 235 val = in_le32(DCSR_CGACRE5); 236 writel(val | 0x00000200, DCSR_CGACRE5); 237 238 val = in_le32(EPU_EPCMPR5); 239 writel(interval_mhz, EPU_EPCMPR5); 240 val = in_le32(EPU_EPCCR5); 241 writel(val | 0x82820000, EPU_EPCCR5); 242 val = in_le32(EPU_EPSMCR5); 243 writel(val | 0x002f0000, EPU_EPSMCR5); 244 val = in_le32(EPU_EPECR5); 245 writel(val | 0x20000000, EPU_EPECR5); 246 val = in_le32(EPU_EPGCR); 247 writel(val | 0x80000000, EPU_EPGCR); 248 } 249 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ 250 251 static void erratum_rcw_src(void) 252 { 253 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) 254 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 255 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; 256 u32 val; 257 258 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); 259 val &= ~DCFG_PORSR1_RCW_SRC; 260 val |= DCFG_PORSR1_RCW_SRC_NOR; 261 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); 262 #endif 263 } 264 265 #define I2C_DEBUG_REG 0x6 266 #define I2C_GLITCH_EN 0x8 267 /* 268 * This erratum requires setting glitch_en bit to enable 269 * digital glitch filter to improve clock stability. 270 */ 271 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 272 static void erratum_a009203(void) 273 { 274 #ifdef CONFIG_SYS_I2C 275 u8 __iomem *ptr; 276 #ifdef I2C1_BASE_ADDR 277 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); 278 279 writeb(I2C_GLITCH_EN, ptr); 280 #endif 281 #ifdef I2C2_BASE_ADDR 282 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); 283 284 writeb(I2C_GLITCH_EN, ptr); 285 #endif 286 #ifdef I2C3_BASE_ADDR 287 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); 288 289 writeb(I2C_GLITCH_EN, ptr); 290 #endif 291 #ifdef I2C4_BASE_ADDR 292 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); 293 294 writeb(I2C_GLITCH_EN, ptr); 295 #endif 296 #endif 297 } 298 #endif 299 300 void bypass_smmu(void) 301 { 302 u32 val; 303 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 304 out_le32(SMMU_SCR0, val); 305 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 306 out_le32(SMMU_NSCR0, val); 307 } 308 void fsl_lsch3_early_init_f(void) 309 { 310 erratum_rcw_src(); 311 #ifdef CONFIG_FSL_IFC 312 init_early_memctl_regs(); /* tighten IFC timing */ 313 #endif 314 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 315 erratum_a009203(); 316 #endif 317 erratum_a008514(); 318 erratum_a008336(); 319 erratum_a009008(); 320 erratum_a009798(); 321 erratum_a008997(); 322 erratum_a009007(); 323 #ifdef CONFIG_CHAIN_OF_TRUST 324 /* In case of Secure Boot, the IBR configures the SMMU 325 * to allow only Secure transactions. 326 * SMMU must be reset in bypass mode. 327 * Set the ClientPD bit and Clear the USFCFG Bit 328 */ 329 if (fsl_check_boot_mode_secure() == 1) 330 bypass_smmu(); 331 #endif 332 } 333 334 #ifdef CONFIG_SCSI_AHCI_PLAT 335 int sata_init(void) 336 { 337 struct ccsr_ahci __iomem *ccsr_ahci; 338 339 #ifdef CONFIG_SYS_SATA2 340 ccsr_ahci = (void *)CONFIG_SYS_SATA2; 341 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 342 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 343 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 344 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 345 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 346 #endif 347 348 #ifdef CONFIG_SYS_SATA1 349 ccsr_ahci = (void *)CONFIG_SYS_SATA1; 350 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 351 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 352 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 353 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 354 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 355 356 ahci_init((void __iomem *)CONFIG_SYS_SATA1); 357 scsi_scan(false); 358 #endif 359 360 return 0; 361 } 362 #endif 363 364 /* Get VDD in the unit mV from voltage ID */ 365 int get_core_volt_from_fuse(void) 366 { 367 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 368 int vdd; 369 u32 fusesr; 370 u8 vid; 371 372 /* get the voltage ID from fuse status register */ 373 fusesr = in_le32(&gur->dcfg_fusesr); 374 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 375 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & 376 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; 377 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { 378 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & 379 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; 380 } 381 debug("%s: VID = 0x%x\n", __func__, vid); 382 switch (vid) { 383 case 0x00: /* VID isn't supported */ 384 vdd = -EINVAL; 385 debug("%s: The VID feature is not supported\n", __func__); 386 break; 387 case 0x08: /* 0.9V silicon */ 388 vdd = 900; 389 break; 390 case 0x10: /* 1.0V silicon */ 391 vdd = 1000; 392 break; 393 default: /* Other core voltage */ 394 vdd = -EINVAL; 395 debug("%s: The VID(%x) isn't supported\n", __func__, vid); 396 break; 397 } 398 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 399 400 return vdd; 401 } 402 403 #elif defined(CONFIG_FSL_LSCH2) 404 #ifdef CONFIG_SCSI_AHCI_PLAT 405 int sata_init(void) 406 { 407 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; 408 409 /* Disable SATA ECC */ 410 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); 411 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 412 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); 413 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); 414 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 415 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); 416 417 ahci_init((void __iomem *)CONFIG_SYS_SATA); 418 scsi_scan(false); 419 420 return 0; 421 } 422 #endif 423 424 static void erratum_a009929(void) 425 { 426 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 427 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 428 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; 429 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); 430 431 rstrqmr1 |= 0x00000400; 432 gur_out32(&gur->rstrqmr1, rstrqmr1); 433 writel(0x01000000, dcsr_cop_ccp); 434 #endif 435 } 436 437 /* 438 * This erratum requires setting a value to eddrtqcr1 to optimal 439 * the DDR performance. The eddrtqcr1 register is in SCFG space 440 * of LS1043A and the offset is 0x157_020c. 441 */ 442 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ 443 && defined(CONFIG_SYS_FSL_ERRATUM_A008514) 444 #error A009660 and A008514 can not be both enabled. 445 #endif 446 447 static void erratum_a009660(void) 448 { 449 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 450 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; 451 out_be32(eddrtqcr1, 0x63b20042); 452 #endif 453 } 454 455 static void erratum_a008850_early(void) 456 { 457 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 458 /* part 1 of 2 */ 459 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 460 CONFIG_SYS_CCI400_OFFSET); 461 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 462 463 /* Skip if running at lower exception level */ 464 if (current_el() < 3) 465 return; 466 467 /* disables propagation of barrier transactions to DDRC from CCI400 */ 468 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 469 470 /* disable the re-ordering in DDRC */ 471 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 472 #endif 473 } 474 475 void erratum_a008850_post(void) 476 { 477 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 478 /* part 2 of 2 */ 479 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 480 CONFIG_SYS_CCI400_OFFSET); 481 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 482 u32 tmp; 483 484 /* Skip if running at lower exception level */ 485 if (current_el() < 3) 486 return; 487 488 /* enable propagation of barrier transactions to DDRC from CCI400 */ 489 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 490 491 /* enable the re-ordering in DDRC */ 492 tmp = ddr_in32(&ddr->eor); 493 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 494 ddr_out32(&ddr->eor, tmp); 495 #endif 496 } 497 498 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 499 void erratum_a010315(void) 500 { 501 int i; 502 503 for (i = PCIE1; i <= PCIE4; i++) 504 if (!is_serdes_configured(i)) { 505 debug("PCIe%d: disabled all R/W permission!\n", i); 506 set_pcie_ns_access(i, 0); 507 } 508 } 509 #endif 510 511 static void erratum_a010539(void) 512 { 513 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) 514 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 515 u32 porsr1; 516 517 porsr1 = in_be32(&gur->porsr1); 518 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; 519 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 520 porsr1); 521 #endif 522 } 523 524 /* Get VDD in the unit mV from voltage ID */ 525 int get_core_volt_from_fuse(void) 526 { 527 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 528 int vdd; 529 u32 fusesr; 530 u8 vid; 531 532 fusesr = in_be32(&gur->dcfg_fusesr); 533 debug("%s: fusesr = 0x%x\n", __func__, fusesr); 534 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & 535 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; 536 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { 537 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & 538 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; 539 } 540 debug("%s: VID = 0x%x\n", __func__, vid); 541 switch (vid) { 542 case 0x00: /* VID isn't supported */ 543 vdd = -EINVAL; 544 debug("%s: The VID feature is not supported\n", __func__); 545 break; 546 case 0x08: /* 0.9V silicon */ 547 vdd = 900; 548 break; 549 case 0x10: /* 1.0V silicon */ 550 vdd = 1000; 551 break; 552 default: /* Other core voltage */ 553 vdd = -EINVAL; 554 printf("%s: The VID(%x) isn't supported\n", __func__, vid); 555 break; 556 } 557 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); 558 559 return vdd; 560 } 561 562 __weak int board_switch_core_volt(u32 vdd) 563 { 564 return 0; 565 } 566 567 static int setup_core_volt(u32 vdd) 568 { 569 return board_setup_core_volt(vdd); 570 } 571 572 #ifdef CONFIG_SYS_FSL_DDR 573 static void ddr_enable_0v9_volt(bool en) 574 { 575 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 576 u32 tmp; 577 578 tmp = ddr_in32(&ddr->ddr_cdr1); 579 580 if (en) 581 tmp |= DDR_CDR1_V0PT9_EN; 582 else 583 tmp &= ~DDR_CDR1_V0PT9_EN; 584 585 ddr_out32(&ddr->ddr_cdr1, tmp); 586 } 587 #endif 588 589 int setup_chip_volt(void) 590 { 591 int vdd; 592 593 vdd = get_core_volt_from_fuse(); 594 /* Nothing to do for silicons doesn't support VID */ 595 if (vdd < 0) 596 return vdd; 597 598 if (setup_core_volt(vdd)) 599 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); 600 #ifdef CONFIG_SYS_HAS_SERDES 601 if (setup_serdes_volt(vdd)) 602 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); 603 #endif 604 605 #ifdef CONFIG_SYS_FSL_DDR 606 if (vdd == 900) 607 ddr_enable_0v9_volt(true); 608 #endif 609 610 return 0; 611 } 612 613 #ifdef CONFIG_FSL_PFE 614 void init_pfe_scfg_dcfg_regs(void) 615 { 616 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 617 u32 ecccr2; 618 619 out_be32(&scfg->pfeasbcr, 620 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); 621 out_be32(&scfg->pfebsbcr, 622 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); 623 624 /* CCI-400 QoS settings for PFE */ 625 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS 626 | SCFG_WR_QOS1_PFE2_QOS)); 627 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS 628 | SCFG_RD_QOS1_PFE2_QOS)); 629 630 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); 631 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, 632 ecccr2 | (unsigned int)DISABLE_PFE_ECC); 633 } 634 #endif 635 636 void fsl_lsch2_early_init_f(void) 637 { 638 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 639 CONFIG_SYS_CCI400_OFFSET); 640 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 641 642 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 643 enable_layerscape_ns_access(); 644 #endif 645 646 #ifdef CONFIG_FSL_IFC 647 init_early_memctl_regs(); /* tighten IFC timing */ 648 #endif 649 650 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) 651 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 652 #endif 653 /* Make SEC reads and writes snoopable */ 654 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | 655 SCFG_SNPCNFGCR_SECWRSNP | 656 SCFG_SNPCNFGCR_SATARDSNP | 657 SCFG_SNPCNFGCR_SATAWRSNP); 658 659 /* 660 * Enable snoop requests and DVM message requests for 661 * Slave insterface S4 (A53 core cluster) 662 */ 663 if (current_el() == 3) { 664 out_le32(&cci->slave[4].snoop_ctrl, 665 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 666 } 667 668 /* Erratum */ 669 erratum_a008850_early(); /* part 1 of 2 */ 670 erratum_a009929(); 671 erratum_a009660(); 672 erratum_a010539(); 673 erratum_a009008(); 674 erratum_a009798(); 675 erratum_a008997(); 676 erratum_a009007(); 677 } 678 #endif 679 680 #ifdef CONFIG_QSPI_AHB_INIT 681 /* Enable 4bytes address support and fast read */ 682 int qspi_ahb_init(void) 683 { 684 u32 *qspi_lut, lut_key, *qspi_key; 685 686 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; 687 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; 688 689 lut_key = in_be32(qspi_key); 690 691 if (lut_key == 0x5af05af0) { 692 /* That means the register is BE */ 693 out_be32(qspi_key, 0x5af05af0); 694 /* Unlock the lut table */ 695 out_be32(qspi_key + 1, 0x00000002); 696 out_be32(qspi_lut, 0x0820040c); 697 out_be32(qspi_lut + 1, 0x1c080c08); 698 out_be32(qspi_lut + 2, 0x00002400); 699 /* Lock the lut table */ 700 out_be32(qspi_key, 0x5af05af0); 701 out_be32(qspi_key + 1, 0x00000001); 702 } else { 703 /* That means the register is LE */ 704 out_le32(qspi_key, 0x5af05af0); 705 /* Unlock the lut table */ 706 out_le32(qspi_key + 1, 0x00000002); 707 out_le32(qspi_lut, 0x0820040c); 708 out_le32(qspi_lut + 1, 0x1c080c08); 709 out_le32(qspi_lut + 2, 0x00002400); 710 /* Lock the lut table */ 711 out_le32(qspi_key, 0x5af05af0); 712 out_le32(qspi_key + 1, 0x00000001); 713 } 714 715 return 0; 716 } 717 #endif 718 719 #ifdef CONFIG_BOARD_LATE_INIT 720 int board_late_init(void) 721 { 722 #ifdef CONFIG_SCSI_AHCI_PLAT 723 sata_init(); 724 #endif 725 #ifdef CONFIG_CHAIN_OF_TRUST 726 fsl_setenv_chain_of_trust(); 727 #endif 728 #ifdef CONFIG_QSPI_AHB_INIT 729 qspi_ahb_init(); 730 #endif 731 732 return 0; 733 } 734 #endif 735