1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #ifdef CONFIG_FSL_CORENET 27 #include <asm/fsl_portals.h> 28 #include <asm/fsl_liodn.h> 29 #include <fsl_qbman.h> 30 #endif 31 #include <fsl_usb.h> 32 #include <hwconfig.h> 33 #include <linux/compiler.h> 34 #include "mp.h" 35 #ifdef CONFIG_CHAIN_OF_TRUST 36 #include <fsl_validate.h> 37 #endif 38 #ifdef CONFIG_FSL_CAAM 39 #include <fsl_sec.h> 40 #endif 41 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) 42 #include <asm/fsl_pamu.h> 43 #include <fsl_secboot_err.h> 44 #endif 45 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 46 #include <nand.h> 47 #include <errno.h> 48 #endif 49 #ifndef CONFIG_ARCH_QEMU_E500 50 #include <fsl_ddr.h> 51 #endif 52 #include "../../../../drivers/ata/fsl_sata.h" 53 #ifdef CONFIG_U_QE 54 #include <fsl_qe.h> 55 #endif 56 57 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 58 /* 59 * For deriving usb clock from 100MHz sysclk, reference divisor is set 60 * to a value of 5, which gives an intermediate value 20(100/5). The 61 * multiplication factor integer is set to 24, which when multiplied to 62 * above intermediate value provides clock for usb ip. 63 */ 64 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 65 { 66 sys_info_t sysinfo; 67 68 get_sys_info(&sysinfo); 69 if (sysinfo.diff_sysclk == 1) { 70 clrbits_be32(&usb_phy->pllprg[1], 71 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 72 setbits_be32(&usb_phy->pllprg[1], 73 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 74 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 75 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 76 } 77 } 78 #endif 79 80 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 81 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 82 { 83 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 84 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 85 86 /* Increase Disconnect Threshold by 50mV */ 87 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 88 INC_DCNT_THRESHOLD_50MV; 89 /* Enable programming of USB High speed Disconnect threshold */ 90 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 91 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 92 93 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 94 /* Increase Disconnect Threshold by 50mV */ 95 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 96 INC_DCNT_THRESHOLD_50MV; 97 /* Enable programming of USB High speed Disconnect threshold */ 98 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 99 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 100 #else 101 102 u32 temp = 0; 103 u32 status = in_be32(&usb_phy->status1); 104 105 u32 squelch_prog_rd_0_2 = 106 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 107 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 108 109 u32 squelch_prog_rd_3_5 = 110 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 111 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 112 113 setbits_be32(&usb_phy->config1, 114 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 115 setbits_be32(&usb_phy->config2, 116 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 117 118 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 119 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 120 121 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 122 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 123 #endif 124 } 125 #endif 126 127 128 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 129 extern qe_iop_conf_t qe_iop_conf_tab[]; 130 extern void qe_config_iopin(u8 port, u8 pin, int dir, 131 int open_drain, int assign); 132 extern void qe_init(uint qe_base); 133 extern void qe_reset(void); 134 135 static void config_qe_ioports(void) 136 { 137 u8 port, pin; 138 int dir, open_drain, assign; 139 int i; 140 141 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 142 port = qe_iop_conf_tab[i].port; 143 pin = qe_iop_conf_tab[i].pin; 144 dir = qe_iop_conf_tab[i].dir; 145 open_drain = qe_iop_conf_tab[i].open_drain; 146 assign = qe_iop_conf_tab[i].assign; 147 qe_config_iopin(port, pin, dir, open_drain, assign); 148 } 149 } 150 #endif 151 152 #ifdef CONFIG_CPM2 153 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 154 { 155 int portnum; 156 157 for (portnum = 0; portnum < 4; portnum++) { 158 uint pmsk = 0, 159 ppar = 0, 160 psor = 0, 161 pdir = 0, 162 podr = 0, 163 pdat = 0; 164 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 165 iop_conf_t *eiopc = iopc + 32; 166 uint msk = 1; 167 168 /* 169 * NOTE: 170 * index 0 refers to pin 31, 171 * index 31 refers to pin 0 172 */ 173 while (iopc < eiopc) { 174 if (iopc->conf) { 175 pmsk |= msk; 176 if (iopc->ppar) 177 ppar |= msk; 178 if (iopc->psor) 179 psor |= msk; 180 if (iopc->pdir) 181 pdir |= msk; 182 if (iopc->podr) 183 podr |= msk; 184 if (iopc->pdat) 185 pdat |= msk; 186 } 187 188 msk <<= 1; 189 iopc++; 190 } 191 192 if (pmsk != 0) { 193 volatile ioport_t *iop = ioport_addr (cpm, portnum); 194 uint tpmsk = ~pmsk; 195 196 /* 197 * the (somewhat confused) paragraph at the 198 * bottom of page 35-5 warns that there might 199 * be "unknown behaviour" when programming 200 * PSORx and PDIRx, if PPARx = 1, so I 201 * decided this meant I had to disable the 202 * dedicated function first, and enable it 203 * last. 204 */ 205 iop->ppar &= tpmsk; 206 iop->psor = (iop->psor & tpmsk) | psor; 207 iop->podr = (iop->podr & tpmsk) | podr; 208 iop->pdat = (iop->pdat & tpmsk) | pdat; 209 iop->pdir = (iop->pdir & tpmsk) | pdir; 210 iop->ppar |= ppar; 211 } 212 } 213 } 214 #endif 215 216 #ifdef CONFIG_SYS_FSL_CPC 217 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 218 void disable_cpc_sram(void) 219 { 220 int i; 221 222 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 223 224 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 225 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 226 /* find and disable LAW of SRAM */ 227 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 228 229 if (law.index == -1) { 230 printf("\nFatal error happened\n"); 231 return; 232 } 233 disable_law(law.index); 234 235 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 236 out_be32(&cpc->cpccsr0, 0); 237 out_be32(&cpc->cpcsrcr0, 0); 238 } 239 } 240 } 241 #endif 242 243 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 244 #ifdef CONFIG_POST 245 #error POST memory test cannot be enabled with TDM 246 #endif 247 static void enable_tdm_law(void) 248 { 249 int ret; 250 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 251 int tdm_hwconfig_enabled = 0; 252 253 /* 254 * Extract hwconfig from environment since environment 255 * is not setup properly yet. Search for tdm entry in 256 * hwconfig. 257 */ 258 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 259 if (ret > 0) { 260 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 261 /* If tdm is defined in hwconfig, set law for tdm workaround */ 262 if (tdm_hwconfig_enabled) 263 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 264 LAW_TRGT_IF_CCSR); 265 } 266 } 267 #endif 268 269 void enable_cpc(void) 270 { 271 int i; 272 int ret; 273 u32 size = 0; 274 u32 cpccfg0; 275 char buffer[HWCONFIG_BUFFER_SIZE]; 276 char cpc_subarg[16]; 277 bool have_hwconfig = false; 278 int cpc_args = 0; 279 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 280 281 /* Extract hwconfig from environment */ 282 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 283 if (ret > 0) { 284 /* 285 * If "en_cpc" is not defined in hwconfig then by default all 286 * cpcs are enable. If this config is defined then individual 287 * cpcs which have to be enabled should also be defined. 288 * e.g en_cpc:cpc1,cpc2; 289 */ 290 if (hwconfig_f("en_cpc", buffer)) 291 have_hwconfig = true; 292 } 293 294 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 295 if (have_hwconfig) { 296 sprintf(cpc_subarg, "cpc%u", i + 1); 297 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 298 if (cpc_args == 0) 299 continue; 300 } 301 cpccfg0 = in_be32(&cpc->cpccfg0); 302 size += CPC_CFG0_SZ_K(cpccfg0); 303 304 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 305 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 306 #endif 307 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 308 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 309 #endif 310 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 311 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 312 #endif 313 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 314 if (has_erratum_a006379()) { 315 setbits_be32(&cpc->cpchdbcr0, 316 CPC_HDBCR0_SPLRU_LEVEL_EN); 317 } 318 #endif 319 320 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 321 /* Read back to sync write */ 322 in_be32(&cpc->cpccsr0); 323 324 } 325 326 puts("Corenet Platform Cache: "); 327 print_size(size * 1024, " enabled\n"); 328 } 329 330 static void invalidate_cpc(void) 331 { 332 int i; 333 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 334 335 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 336 /* skip CPC when it used as all SRAM */ 337 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 338 continue; 339 /* Flash invalidate the CPC and clear all the locks */ 340 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 341 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 342 ; 343 } 344 } 345 #else 346 #define enable_cpc() 347 #define invalidate_cpc() 348 #define disable_cpc_sram() 349 #endif /* CONFIG_SYS_FSL_CPC */ 350 351 /* 352 * Breathe some life into the CPU... 353 * 354 * Set up the memory map 355 * initialize a bunch of registers 356 */ 357 358 #ifdef CONFIG_FSL_CORENET 359 static void corenet_tb_init(void) 360 { 361 volatile ccsr_rcpm_t *rcpm = 362 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 363 volatile ccsr_pic_t *pic = 364 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 365 u32 whoami = in_be32(&pic->whoami); 366 367 /* Enable the timebase register for this core */ 368 out_be32(&rcpm->ctbenrl, (1 << whoami)); 369 } 370 #endif 371 372 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 373 void fsl_erratum_a007212_workaround(void) 374 { 375 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 376 u32 ddr_pll_ratio; 377 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 378 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 379 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 380 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 381 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 382 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 383 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 384 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 385 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 386 #endif 387 #endif 388 /* 389 * Even this workaround applies to selected version of SoCs, it is 390 * safe to apply to all versions, with the limitation of odd ratios. 391 * If RCW has disabled DDR PLL, we have to apply this workaround, 392 * otherwise DDR will not work. 393 */ 394 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 395 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 396 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 397 /* check if RCW sets ratio to 0, required by this workaround */ 398 if (ddr_pll_ratio != 0) 399 return; 400 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 401 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 402 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 403 /* check if reserved bits have the desired ratio */ 404 if (ddr_pll_ratio == 0) { 405 printf("Error: Unknown DDR PLL ratio!\n"); 406 return; 407 } 408 ddr_pll_ratio >>= 1; 409 410 setbits_be32(plldadcr1, 0x02000001); 411 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 412 setbits_be32(plldadcr2, 0x02000001); 413 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 414 setbits_be32(plldadcr3, 0x02000001); 415 #endif 416 #endif 417 setbits_be32(dpdovrcr4, 0xe0000000); 418 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 419 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 420 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 421 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 422 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 423 #endif 424 #endif 425 udelay(100); 426 clrbits_be32(plldadcr1, 0x02000001); 427 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 428 clrbits_be32(plldadcr2, 0x02000001); 429 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 430 clrbits_be32(plldadcr3, 0x02000001); 431 #endif 432 #endif 433 clrbits_be32(dpdovrcr4, 0xe0000000); 434 } 435 #endif 436 437 ulong cpu_init_f(void) 438 { 439 extern void m8560_cpm_reset (void); 440 #ifdef CONFIG_SYS_DCSRBAR_PHYS 441 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 442 #endif 443 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) 444 struct law_entry law; 445 #endif 446 #ifdef CONFIG_ARCH_MPC8548 447 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 448 uint svr = get_svr(); 449 450 /* 451 * CPU2 errata workaround: A core hang possible while executing 452 * a msync instruction and a snoopable transaction from an I/O 453 * master tagged to make quick forward progress is present. 454 * Fixed in silicon rev 2.1. 455 */ 456 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 457 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 458 #endif 459 460 disable_tlb(14); 461 disable_tlb(15); 462 463 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) 464 /* Disable the LAW created for NOR flash by the PBI commands */ 465 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 466 if (law.index != -1) 467 disable_law(law.index); 468 469 #if defined(CONFIG_SYS_CPC_REINIT_F) 470 disable_cpc_sram(); 471 #endif 472 #endif 473 474 #ifdef CONFIG_CPM2 475 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 476 #endif 477 478 init_early_memctl_regs(); 479 480 #if defined(CONFIG_CPM2) 481 m8560_cpm_reset(); 482 #endif 483 484 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 485 /* Config QE ioports */ 486 config_qe_ioports(); 487 #endif 488 489 #if defined(CONFIG_FSL_DMA) 490 dma_init(); 491 #endif 492 #ifdef CONFIG_FSL_CORENET 493 corenet_tb_init(); 494 #endif 495 init_used_tlb_cams(); 496 497 /* Invalidate the CPC before DDR gets enabled */ 498 invalidate_cpc(); 499 500 #ifdef CONFIG_SYS_DCSRBAR_PHYS 501 /* set DCSRCR so that DCSR space is 1G */ 502 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 503 in_be32(&gur->dcsrcr); 504 #endif 505 506 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 507 fsl_erratum_a007212_workaround(); 508 #endif 509 510 return 0; 511 } 512 513 /* Implement a dummy function for those platforms w/o SERDES */ 514 static void __fsl_serdes__init(void) 515 { 516 return ; 517 } 518 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 519 520 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 521 int enable_cluster_l2(void) 522 { 523 int i = 0; 524 u32 cluster, svr = get_svr(); 525 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 526 struct ccsr_cluster_l2 __iomem *l2cache; 527 528 /* only the L2 of first cluster should be enabled as expected on T4080, 529 * but there is no EOC in the first cluster as HW sake, so return here 530 * to skip enabling L2 cache of the 2nd cluster. 531 */ 532 if (SVR_SOC_VER(svr) == SVR_T4080) 533 return 0; 534 535 cluster = in_be32(&gur->tp_cluster[i].lower); 536 if (cluster & TP_CLUSTER_EOC) 537 return 0; 538 539 /* The first cache has already been set up, so skip it */ 540 i++; 541 542 /* Look through the remaining clusters, and set up their caches */ 543 do { 544 int j, cluster_valid = 0; 545 546 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 547 548 cluster = in_be32(&gur->tp_cluster[i].lower); 549 550 /* check that at least one core/accel is enabled in cluster */ 551 for (j = 0; j < 4; j++) { 552 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 553 u32 type = in_be32(&gur->tp_ityp[idx]); 554 555 if ((type & TP_ITYP_AV) && 556 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 557 cluster_valid = 1; 558 } 559 560 if (cluster_valid) { 561 /* set stash ID to (cluster) * 2 + 32 + 1 */ 562 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 563 564 printf("enable l2 for cluster %d %p\n", i, l2cache); 565 566 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 567 while ((in_be32(&l2cache->l2csr0) 568 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 569 ; 570 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 571 } 572 i++; 573 } while (!(cluster & TP_CLUSTER_EOC)); 574 575 return 0; 576 } 577 #endif 578 579 /* 580 * Initialize L2 as cache. 581 */ 582 int l2cache_init(void) 583 { 584 __maybe_unused u32 svr = get_svr(); 585 #ifdef CONFIG_L2_CACHE 586 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 587 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 588 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 589 #endif 590 591 puts ("L2: "); 592 593 #if defined(CONFIG_L2_CACHE) 594 volatile uint cache_ctl; 595 uint ver; 596 u32 l2siz_field; 597 598 ver = SVR_SOC_VER(svr); 599 600 asm("msync;isync"); 601 cache_ctl = l2cache->l2ctl; 602 603 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 604 if (cache_ctl & MPC85xx_L2CTL_L2E) { 605 /* Clear L2 SRAM memory-mapped base address */ 606 out_be32(&l2cache->l2srbar0, 0x0); 607 out_be32(&l2cache->l2srbar1, 0x0); 608 609 /* set MBECCDIS=0, SBECCDIS=0 */ 610 clrbits_be32(&l2cache->l2errdis, 611 (MPC85xx_L2ERRDIS_MBECC | 612 MPC85xx_L2ERRDIS_SBECC)); 613 614 /* set L2E=0, L2SRAM=0 */ 615 clrbits_be32(&l2cache->l2ctl, 616 (MPC85xx_L2CTL_L2E | 617 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 618 } 619 #endif 620 621 l2siz_field = (cache_ctl >> 28) & 0x3; 622 623 switch (l2siz_field) { 624 case 0x0: 625 printf(" unknown size (0x%08x)\n", cache_ctl); 626 return -1; 627 break; 628 case 0x1: 629 if (ver == SVR_8540 || ver == SVR_8560 || 630 ver == SVR_8541 || ver == SVR_8555) { 631 puts("128 KiB "); 632 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 633 cache_ctl = 0xc4000000; 634 } else { 635 puts("256 KiB "); 636 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 637 } 638 break; 639 case 0x2: 640 if (ver == SVR_8540 || ver == SVR_8560 || 641 ver == SVR_8541 || ver == SVR_8555) { 642 puts("256 KiB "); 643 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 644 cache_ctl = 0xc8000000; 645 } else { 646 puts("512 KiB "); 647 /* set L2E=1, L2I=1, & L2SRAM=0 */ 648 cache_ctl = 0xc0000000; 649 } 650 break; 651 case 0x3: 652 puts("1024 KiB "); 653 /* set L2E=1, L2I=1, & L2SRAM=0 */ 654 cache_ctl = 0xc0000000; 655 break; 656 } 657 658 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 659 puts("already enabled"); 660 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 661 u32 l2srbar = l2cache->l2srbar0; 662 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 663 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 664 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 665 l2cache->l2srbar0 = l2srbar; 666 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 667 } 668 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 669 puts("\n"); 670 } else { 671 asm("msync;isync"); 672 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 673 asm("msync;isync"); 674 puts("enabled\n"); 675 } 676 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 677 if (SVR_SOC_VER(svr) == SVR_P2040) { 678 puts("N/A\n"); 679 goto skip_l2; 680 } 681 682 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 683 684 /* invalidate the L2 cache */ 685 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 686 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 687 ; 688 689 #ifdef CONFIG_SYS_CACHE_STASHING 690 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 691 mtspr(SPRN_L2CSR1, (32 + 1)); 692 #endif 693 694 /* enable the cache */ 695 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 696 697 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 698 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 699 ; 700 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 701 } 702 703 skip_l2: 704 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 705 if (l2cache->l2csr0 & L2CSR0_L2E) 706 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 707 " enabled\n"); 708 709 enable_cluster_l2(); 710 #else 711 puts("disabled\n"); 712 #endif 713 714 return 0; 715 } 716 717 /* 718 * 719 * The newer 8548, etc, parts have twice as much cache, but 720 * use the same bit-encoding as the older 8555, etc, parts. 721 * 722 */ 723 int cpu_init_r(void) 724 { 725 __maybe_unused u32 svr = get_svr(); 726 #ifdef CONFIG_SYS_LBC_LCRR 727 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 728 #endif 729 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 730 extern int spin_table_compat; 731 const char *spin; 732 #endif 733 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 734 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 735 #endif 736 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 737 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 738 /* 739 * CPU22 and NMG_CPU_A011 share the same workaround. 740 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 741 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 742 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 743 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 744 * be disabled by hwconfig with syntax: 745 * 746 * fsl_cpu_a011:disable 747 */ 748 extern int enable_cpu_a011_workaround; 749 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 750 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 751 #else 752 char buffer[HWCONFIG_BUFFER_SIZE]; 753 char *buf = NULL; 754 int n, res; 755 756 n = env_get_f("hwconfig", buffer, sizeof(buffer)); 757 if (n > 0) 758 buf = buffer; 759 760 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 761 if (res > 0) { 762 enable_cpu_a011_workaround = 0; 763 } else { 764 if (n >= HWCONFIG_BUFFER_SIZE) { 765 printf("fsl_cpu_a011 was not found. hwconfig variable " 766 "may be too long\n"); 767 } 768 enable_cpu_a011_workaround = 769 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 770 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 771 } 772 #endif 773 if (enable_cpu_a011_workaround) { 774 flush_dcache(); 775 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 776 sync(); 777 } 778 #endif 779 780 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907 781 flush_dcache(); 782 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); 783 sync(); 784 #endif 785 786 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 787 /* 788 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 789 * in write shadow mode. Checking DCWS before setting SPR 976. 790 */ 791 if (mfspr(L1CSR2) & L1CSR2_DCWS) 792 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 793 #endif 794 795 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 796 spin = env_get("spin_table_compat"); 797 if (spin && (*spin == 'n')) 798 spin_table_compat = 0; 799 else 800 spin_table_compat = 1; 801 #endif 802 803 #ifdef CONFIG_FSL_CORENET 804 set_liodns(); 805 #ifdef CONFIG_SYS_DPAA_QBMAN 806 setup_qbman_portals(); 807 #endif 808 #endif 809 810 l2cache_init(); 811 #if defined(CONFIG_RAMBOOT_PBL) 812 disable_cpc_sram(); 813 #endif 814 enable_cpc(); 815 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 816 enable_tdm_law(); 817 #endif 818 819 #ifndef CONFIG_SYS_FSL_NO_SERDES 820 /* needs to be in ram since code uses global static vars */ 821 fsl_serdes_init(); 822 #endif 823 824 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 825 #define MCFGR_AXIPIPE 0x000000f0 826 if (IS_SVR_REV(svr, 1, 0)) 827 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); 828 #endif 829 830 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 831 if (IS_SVR_REV(svr, 1, 0)) { 832 int i; 833 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 834 835 for (i = 0; i < 12; i++) { 836 p += i + (i > 5 ? 11 : 0); 837 out_be32(p, 0x2); 838 } 839 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 840 out_be32(p, 0x34); 841 } 842 #endif 843 844 #ifdef CONFIG_SYS_SRIO 845 srio_init(); 846 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 847 char *s = env_get("bootmaster"); 848 if (s) { 849 if (!strcmp(s, "SRIO1")) { 850 srio_boot_master(1); 851 srio_boot_master_release_slave(1); 852 } 853 if (!strcmp(s, "SRIO2")) { 854 srio_boot_master(2); 855 srio_boot_master_release_slave(2); 856 } 857 } 858 #endif 859 #endif 860 861 #if defined(CONFIG_MP) 862 setup_mp(); 863 #endif 864 865 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 866 { 867 if (SVR_MAJ(svr) < 3) { 868 void *p; 869 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 870 setbits_be32(p, 1 << (31 - 14)); 871 } 872 } 873 #endif 874 875 #ifdef CONFIG_SYS_LBC_LCRR 876 /* 877 * Modify the CLKDIV field of LCRR register to improve the writing 878 * speed for NOR flash. 879 */ 880 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 881 __raw_readl(&lbc->lcrr); 882 isync(); 883 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 884 udelay(100); 885 #endif 886 #endif 887 888 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 889 { 890 struct ccsr_usb_phy __iomem *usb_phy1 = 891 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 892 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 893 if (has_erratum_a006261()) 894 fsl_erratum_a006261_workaround(usb_phy1); 895 #endif 896 out_be32(&usb_phy1->usb_enable_override, 897 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 898 } 899 #endif 900 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 901 { 902 struct ccsr_usb_phy __iomem *usb_phy2 = 903 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 904 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 905 if (has_erratum_a006261()) 906 fsl_erratum_a006261_workaround(usb_phy2); 907 #endif 908 out_be32(&usb_phy2->usb_enable_override, 909 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 910 } 911 #endif 912 913 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 914 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 915 * multi-bit ECC errors which has impact on performance, so software 916 * should disable all ECC reporting from USB1 and USB2. 917 */ 918 if (IS_SVR_REV(get_svr(), 1, 0)) { 919 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 920 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 921 setbits_be32(&dcfg->ecccr1, 922 (DCSR_DCFG_ECC_DISABLE_USB1 | 923 DCSR_DCFG_ECC_DISABLE_USB2)); 924 } 925 #endif 926 927 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 928 struct ccsr_usb_phy __iomem *usb_phy = 929 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 930 setbits_be32(&usb_phy->pllprg[1], 931 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 932 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 933 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 934 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 935 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 936 usb_single_source_clk_configure(usb_phy); 937 #endif 938 setbits_be32(&usb_phy->port1.ctrl, 939 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 940 setbits_be32(&usb_phy->port1.drvvbuscfg, 941 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 942 setbits_be32(&usb_phy->port1.pwrfltcfg, 943 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 944 setbits_be32(&usb_phy->port2.ctrl, 945 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 946 setbits_be32(&usb_phy->port2.drvvbuscfg, 947 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 948 setbits_be32(&usb_phy->port2.pwrfltcfg, 949 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 950 951 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 952 if (has_erratum_a006261()) 953 fsl_erratum_a006261_workaround(usb_phy); 954 #endif 955 956 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 957 958 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 959 erratum_a009942_check_cpo(); 960 #endif 961 962 #ifdef CONFIG_FMAN_ENET 963 fman_enet_init(); 964 #endif 965 966 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) 967 if (pamu_init() < 0) 968 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); 969 #endif 970 971 #ifdef CONFIG_FSL_CAAM 972 sec_init(); 973 974 #if defined(CONFIG_ARCH_C29X) 975 if ((SVR_SOC_VER(svr) == SVR_C292) || 976 (SVR_SOC_VER(svr) == SVR_C293)) 977 sec_init_idx(1); 978 979 if (SVR_SOC_VER(svr) == SVR_C293) 980 sec_init_idx(2); 981 #endif 982 #endif 983 984 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) 985 /* 986 * For P1022/1013 Rev1.0 silicon, after power on SATA host 987 * controller is configured in legacy mode instead of the 988 * expected enterprise mode. Software needs to clear bit[28] 989 * of HControl register to change to enterprise mode from 990 * legacy mode. We assume that the controller is offline. 991 */ 992 if (IS_SVR_REV(svr, 1, 0) && 993 ((SVR_SOC_VER(svr) == SVR_P1022) || 994 (SVR_SOC_VER(svr) == SVR_P1013))) { 995 fsl_sata_reg_t *reg; 996 997 /* first SATA controller */ 998 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 999 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 1000 1001 /* second SATA controller */ 1002 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 1003 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 1004 } 1005 #endif 1006 1007 init_used_tlb_cams(); 1008 1009 return 0; 1010 } 1011 1012 void arch_preboot_os(void) 1013 { 1014 u32 msr; 1015 1016 /* 1017 * We are changing interrupt offsets and are about to boot the OS so 1018 * we need to make sure we disable all async interrupts. EE is already 1019 * disabled by the time we get called. 1020 */ 1021 msr = mfmsr(); 1022 msr &= ~(MSR_ME|MSR_CE); 1023 mtmsr(msr); 1024 } 1025 1026 #if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA) 1027 int sata_initialize(void) 1028 { 1029 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 1030 return __sata_initialize(); 1031 1032 return 1; 1033 } 1034 #endif 1035 1036 void cpu_secondary_init_r(void) 1037 { 1038 #ifdef CONFIG_U_QE 1039 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 1040 #elif defined CONFIG_QE 1041 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 1042 #endif 1043 1044 #ifdef CONFIG_QE 1045 qe_init(qe_base); 1046 qe_reset(); 1047 #endif 1048 } 1049 1050 #ifdef CONFIG_BOARD_LATE_INIT 1051 int board_late_init(void) 1052 { 1053 #ifdef CONFIG_CHAIN_OF_TRUST 1054 fsl_setenv_chain_of_trust(); 1055 #endif 1056 1057 return 0; 1058 } 1059 #endif 1060