1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 */
10
11 #include <common.h>
12 #include <watchdog.h>
13 #include <asm/immap.h>
14 #include <asm/io.h>
15
16 #if defined(CONFIG_CMD_NET)
17 #include <config.h>
18 #include <net.h>
19 #include <asm/fec.h>
20 #endif
21
22 /* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
23 #ifdef CONFIG_M5235
24 #define out_be_fbcs_reg out_be16
25 #else
26 #define out_be_fbcs_reg out_be32
27 #endif
28
29 /*
30 * Breath some life into the CPU...
31 *
32 * Set up the memory map,
33 * initialize a bunch of registers,
34 * initialize the UPM's
35 */
cpu_init_f(void)36 void cpu_init_f(void)
37 {
38 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
39 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
40 wdog_t *wdog = (wdog_t *) MMAP_WDOG;
41 scm_t *scm = (scm_t *) MMAP_SCM;
42
43 /* watchdog is enabled by default - disable the watchdog */
44 #ifndef CONFIG_WATCHDOG
45 out_be16(&wdog->cr, 0);
46 #endif
47
48 out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
49
50 /* Port configuration */
51 out_8(&gpio->par_cs, 0);
52
53 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
54 out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
55 out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
56 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
57 #endif
58
59 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
60 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
61 out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
62 out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
63 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
64 #endif
65
66 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
67 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
68 out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
69 out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
70 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
71 #endif
72
73 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
74 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
75 out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
76 out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
77 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
78 #endif
79
80 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
81 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
82 out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
83 out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
84 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
85 #endif
86
87 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
88 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
89 out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
90 out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
91 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
92 #endif
93
94 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
95 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
96 out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
97 out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
98 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
99 #endif
100
101 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
102 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
103 out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
104 out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
105 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
106 #endif
107
108 #ifdef CONFIG_SYS_I2C_FSL
109 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
110 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
111 #endif
112
113 icache_enable();
114 }
115
116 /*
117 * initialize higher level parts of CPU like timers
118 */
cpu_init_r(void)119 int cpu_init_r(void)
120 {
121 return (0);
122 }
123
uart_port_conf(int port)124 void uart_port_conf(int port)
125 {
126 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
127
128 /* Setup Ports: */
129 switch (port) {
130 case 0:
131 clrbits_be16(&gpio->par_uart,
132 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
133 setbits_be16(&gpio->par_uart,
134 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
135 break;
136 case 1:
137 clrbits_be16(&gpio->par_uart,
138 GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
139 setbits_be16(&gpio->par_uart,
140 GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
141 break;
142 case 2:
143 #ifdef CONFIG_SYS_UART2_PRI_GPIO
144 clrbits_be16(&gpio->par_uart,
145 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
146 setbits_be16(&gpio->par_uart,
147 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
148 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
149 clrbits_8(&gpio->par_feci2c,
150 GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
151 setbits_8(&gpio->par_feci2c,
152 GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
153 #endif
154 break;
155 }
156 }
157
158 #if defined(CONFIG_CMD_NET)
fecpin_setclear(struct eth_device * dev,int setclear)159 int fecpin_setclear(struct eth_device *dev, int setclear)
160 {
161 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
162
163 if (setclear) {
164 setbits_8(&gpio->par_feci2c,
165 GPIO_PAR_FECI2C_EMDC_FECEMDC |
166 GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
167 } else {
168 clrbits_8(&gpio->par_feci2c,
169 GPIO_PAR_FECI2C_EMDC_MASK |
170 GPIO_PAR_FECI2C_EMDIO_MASK);
171 }
172
173 return 0;
174 }
175 #endif
176