1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cru_rk3188.h> 18 #include <asm/arch/grf_rk3188.h> 19 #include <asm/arch/hardware.h> 20 #include <dt-bindings/clock/rk3188-cru.h> 21 #include <dm/device-internal.h> 22 #include <dm/lists.h> 23 #include <dm/uclass-internal.h> 24 #include <linux/log2.h> 25 26 enum rk3188_clk_type { 27 RK3188_CRU, 28 RK3188A_CRU, 29 }; 30 31 struct rk3188_clk_plat { 32 #if CONFIG_IS_ENABLED(OF_PLATDATA) 33 struct dtd_rockchip_rk3188_cru dtd; 34 #endif 35 }; 36 37 struct pll_div { 38 u32 nr; 39 u32 nf; 40 u32 no; 41 }; 42 43 enum { 44 VCO_MAX_HZ = 2200U * 1000000, 45 VCO_MIN_HZ = 440 * 1000000, 46 OUTPUT_MAX_HZ = 2200U * 1000000, 47 OUTPUT_MIN_HZ = 30 * 1000000, 48 FREF_MAX_HZ = 2200U * 1000000, 49 FREF_MIN_HZ = 30 * 1000, 50 }; 51 52 enum { 53 /* PLL CON0 */ 54 PLL_OD_MASK = 0x0f, 55 56 /* PLL CON1 */ 57 PLL_NF_MASK = 0x1fff, 58 59 /* PLL CON2 */ 60 PLL_BWADJ_MASK = 0x0fff, 61 62 /* PLL CON3 */ 63 PLL_RESET_SHIFT = 5, 64 65 /* GRF_SOC_STATUS0 */ 66 SOCSTS_DPLL_LOCK = 1 << 5, 67 SOCSTS_APLL_LOCK = 1 << 6, 68 SOCSTS_CPLL_LOCK = 1 << 7, 69 SOCSTS_GPLL_LOCK = 1 << 8, 70 }; 71 72 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 73 74 #define PLL_DIVISORS(hz, _nr, _no) {\ 75 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ 76 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ 77 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ 78 "divisors on line " __stringify(__LINE__)); 79 80 /* Keep divisors as low as possible to reduce jitter and power usage */ 81 #ifdef CONFIG_SPL_BUILD 82 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); 83 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); 84 #endif 85 86 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, 87 const struct pll_div *div, bool has_bwadj) 88 { 89 int pll_id = rk_pll_id(clk_id); 90 struct rk3188_pll *pll = &cru->pll[pll_id]; 91 /* All PLLs have same VCO and output frequency range restrictions. */ 92 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; 93 uint output_hz = vco_hz / div->no; 94 95 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", 96 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); 97 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 98 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && 99 (div->no == 1 || !(div->no % 2))); 100 101 /* enter reset */ 102 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); 103 104 rk_clrsetreg(&pll->con0, 105 CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, 106 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); 107 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); 108 109 if (has_bwadj) 110 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); 111 112 udelay(10); 113 114 /* return from reset */ 115 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); 116 117 return 0; 118 } 119 120 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, 121 unsigned int hz, bool has_bwadj) 122 { 123 static const struct pll_div dpll_cfg[] = { 124 {.nf = 75, .nr = 1, .no = 6}, 125 {.nf = 400, .nr = 9, .no = 2}, 126 {.nf = 500, .nr = 9, .no = 2}, 127 {.nf = 100, .nr = 3, .no = 1}, 128 }; 129 int cfg; 130 131 switch (hz) { 132 case 300000000: 133 cfg = 0; 134 break; 135 case 533000000: /* actually 533.3P MHz */ 136 cfg = 1; 137 break; 138 case 666000000: /* actually 666.6P MHz */ 139 cfg = 2; 140 break; 141 case 800000000: 142 cfg = 3; 143 break; 144 default: 145 debug("Unsupported SDRAM frequency"); 146 return -EINVAL; 147 } 148 149 /* pll enter slow-mode */ 150 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, 151 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 152 153 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); 154 155 /* wait for pll lock */ 156 while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) 157 udelay(1); 158 159 /* PLL enter normal-mode */ 160 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, 161 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); 162 163 return 0; 164 } 165 166 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, 167 unsigned int hz, bool has_bwadj) 168 { 169 static const struct pll_div apll_cfg[] = { 170 {.nf = 50, .nr = 1, .no = 2}, 171 {.nf = 67, .nr = 1, .no = 1}, 172 }; 173 int div_core_peri, div_aclk_core, cfg; 174 175 /* 176 * We support two possible frequencies, the safe 600MHz 177 * which will work with default pmic settings and will 178 * be set in SPL to get away from the 24MHz default and 179 * the maximum of 1.6Ghz, which boards can set if they 180 * were able to get pmic support for it. 181 */ 182 switch (hz) { 183 case APLL_SAFE_HZ: 184 cfg = 0; 185 div_core_peri = 1; 186 div_aclk_core = 3; 187 break; 188 case APLL_HZ: 189 cfg = 1; 190 div_core_peri = 2; 191 div_aclk_core = 3; 192 break; 193 default: 194 debug("Unsupported ARMCLK frequency"); 195 return -EINVAL; 196 } 197 198 /* pll enter slow-mode */ 199 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, 200 APLL_MODE_SLOW << APLL_MODE_SHIFT); 201 202 rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); 203 204 /* waiting for pll lock */ 205 while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) 206 udelay(1); 207 208 /* Set divider for peripherals attached to the cpu core. */ 209 rk_clrsetreg(&cru->cru_clksel_con[0], 210 CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, 211 div_core_peri << CORE_PERI_DIV_SHIFT); 212 213 /* set up dependent divisor for aclk_core */ 214 rk_clrsetreg(&cru->cru_clksel_con[1], 215 CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT, 216 div_aclk_core << CORE_ACLK_DIV_SHIFT); 217 218 /* PLL enter normal-mode */ 219 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, 220 APLL_MODE_NORMAL << APLL_MODE_SHIFT); 221 222 return hz; 223 } 224 225 /* Get pll rate by id */ 226 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, 227 enum rk_clk_id clk_id) 228 { 229 uint32_t nr, no, nf; 230 uint32_t con; 231 int pll_id = rk_pll_id(clk_id); 232 struct rk3188_pll *pll = &cru->pll[pll_id]; 233 static u8 clk_shift[CLK_COUNT] = { 234 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 235 GPLL_MODE_SHIFT 236 }; 237 uint shift; 238 239 con = readl(&cru->cru_mode_con); 240 shift = clk_shift[clk_id]; 241 switch ((con >> shift) & APLL_MODE_MASK) { 242 case APLL_MODE_SLOW: 243 return OSC_HZ; 244 case APLL_MODE_NORMAL: 245 /* normal mode */ 246 con = readl(&pll->con0); 247 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; 248 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; 249 con = readl(&pll->con1); 250 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; 251 252 return (24 * nf / (nr * no)) * 1000000; 253 case APLL_MODE_DEEP: 254 default: 255 return 32768; 256 } 257 } 258 259 static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, 260 int periph) 261 { 262 uint div; 263 u32 con; 264 265 switch (periph) { 266 case HCLK_EMMC: 267 case SCLK_EMMC: 268 con = readl(&cru->cru_clksel_con[12]); 269 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; 270 break; 271 case HCLK_SDMMC: 272 case SCLK_SDMMC: 273 con = readl(&cru->cru_clksel_con[11]); 274 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; 275 break; 276 case HCLK_SDIO: 277 case SCLK_SDIO: 278 con = readl(&cru->cru_clksel_con[12]); 279 div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK; 280 break; 281 default: 282 return -EINVAL; 283 } 284 285 return DIV_TO_RATE(gclk_rate, div) / 2; 286 } 287 288 static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, 289 int periph, uint freq) 290 { 291 int src_clk_div; 292 293 debug("%s: gclk_rate=%u\n", __func__, gclk_rate); 294 /* mmc clock defaulg div 2 internal, need provide double in cru */ 295 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1; 296 assert(src_clk_div <= 0x3f); 297 298 switch (periph) { 299 case HCLK_EMMC: 300 case SCLK_EMMC: 301 rk_clrsetreg(&cru->cru_clksel_con[12], 302 EMMC_DIV_MASK << EMMC_DIV_SHIFT, 303 src_clk_div << EMMC_DIV_SHIFT); 304 break; 305 case HCLK_SDMMC: 306 case SCLK_SDMMC: 307 rk_clrsetreg(&cru->cru_clksel_con[11], 308 MMC0_DIV_MASK << MMC0_DIV_SHIFT, 309 src_clk_div << MMC0_DIV_SHIFT); 310 break; 311 case HCLK_SDIO: 312 case SCLK_SDIO: 313 rk_clrsetreg(&cru->cru_clksel_con[12], 314 SDIO_DIV_MASK << SDIO_DIV_SHIFT, 315 src_clk_div << SDIO_DIV_SHIFT); 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 return rockchip_mmc_get_clk(cru, gclk_rate, periph); 322 } 323 324 static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate, 325 int periph) 326 { 327 uint div; 328 u32 con; 329 330 switch (periph) { 331 case SCLK_SPI0: 332 con = readl(&cru->cru_clksel_con[25]); 333 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; 334 break; 335 case SCLK_SPI1: 336 con = readl(&cru->cru_clksel_con[25]); 337 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; 338 break; 339 default: 340 return -EINVAL; 341 } 342 343 return DIV_TO_RATE(gclk_rate, div); 344 } 345 346 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, 347 int periph, uint freq) 348 { 349 int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; 350 351 assert(src_clk_div < 128); 352 switch (periph) { 353 case SCLK_SPI0: 354 assert(src_clk_div <= SPI0_DIV_MASK); 355 rk_clrsetreg(&cru->cru_clksel_con[25], 356 SPI0_DIV_MASK << SPI0_DIV_SHIFT, 357 src_clk_div << SPI0_DIV_SHIFT); 358 break; 359 case SCLK_SPI1: 360 assert(src_clk_div <= SPI1_DIV_MASK); 361 rk_clrsetreg(&cru->cru_clksel_con[25], 362 SPI1_DIV_MASK << SPI1_DIV_SHIFT, 363 src_clk_div << SPI1_DIV_SHIFT); 364 break; 365 default: 366 return -EINVAL; 367 } 368 369 return rockchip_spi_get_clk(cru, gclk_rate, periph); 370 } 371 372 #ifdef CONFIG_SPL_BUILD 373 static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, 374 bool has_bwadj) 375 { 376 u32 aclk_div, hclk_div, pclk_div, h2p_div; 377 378 /* pll enter slow-mode */ 379 rk_clrsetreg(&cru->cru_mode_con, 380 GPLL_MODE_MASK << GPLL_MODE_SHIFT | 381 CPLL_MODE_MASK << CPLL_MODE_SHIFT, 382 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 383 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 384 385 /* init pll */ 386 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj); 387 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj); 388 389 /* waiting for pll lock */ 390 while ((readl(&grf->soc_status0) & 391 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != 392 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) 393 udelay(1); 394 395 /* 396 * cpu clock pll source selection and 397 * reparent aclk_cpu_pre from apll to gpll 398 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 399 */ 400 aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; 401 assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 402 403 rk_clrsetreg(&cru->cru_clksel_con[0], 404 CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT | 405 A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT, 406 CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT | 407 aclk_div << A9_CPU_DIV_SHIFT); 408 409 hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); 410 assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); 411 pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); 412 assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); 413 h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ); 414 assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); 415 416 rk_clrsetreg(&cru->cru_clksel_con[1], 417 AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT | 418 CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | 419 CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, 420 h2p_div << AHB2APB_DIV_SHIFT | 421 pclk_div << CPU_PCLK_DIV_SHIFT | 422 hclk_div << CPU_HCLK_DIV_SHIFT); 423 424 /* 425 * peri clock pll source selection and 426 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 427 */ 428 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 429 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 430 431 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 432 assert((1 << hclk_div) * PERI_HCLK_HZ == 433 PERI_ACLK_HZ && (hclk_div < 0x4)); 434 435 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 436 assert((1 << pclk_div) * PERI_PCLK_HZ == 437 PERI_ACLK_HZ && (pclk_div < 0x4)); 438 439 rk_clrsetreg(&cru->cru_clksel_con[10], 440 PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | 441 PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | 442 PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, 443 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | 444 pclk_div << PERI_PCLK_DIV_SHIFT | 445 hclk_div << PERI_HCLK_DIV_SHIFT | 446 aclk_div << PERI_ACLK_DIV_SHIFT); 447 448 /* PLL enter normal-mode */ 449 rk_clrsetreg(&cru->cru_mode_con, 450 GPLL_MODE_MASK << GPLL_MODE_SHIFT | 451 CPLL_MODE_MASK << CPLL_MODE_SHIFT, 452 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | 453 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 454 455 rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000); 456 } 457 #endif 458 459 static ulong rk3188_clk_get_rate(struct clk *clk) 460 { 461 struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); 462 ulong new_rate, gclk_rate; 463 464 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 465 switch (clk->id) { 466 case 1 ... 4: 467 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); 468 break; 469 case HCLK_EMMC: 470 case HCLK_SDMMC: 471 case HCLK_SDIO: 472 case SCLK_EMMC: 473 case SCLK_SDMMC: 474 case SCLK_SDIO: 475 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, 476 clk->id); 477 break; 478 case SCLK_SPI0: 479 case SCLK_SPI1: 480 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, 481 clk->id); 482 break; 483 case PCLK_I2C0: 484 case PCLK_I2C1: 485 case PCLK_I2C2: 486 case PCLK_I2C3: 487 case PCLK_I2C4: 488 return gclk_rate; 489 default: 490 return -ENOENT; 491 } 492 493 return new_rate; 494 } 495 496 static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) 497 { 498 struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); 499 struct rk3188_cru *cru = priv->cru; 500 ulong new_rate; 501 502 switch (clk->id) { 503 case PLL_APLL: 504 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, 505 priv->has_bwadj); 506 break; 507 case CLK_DDR: 508 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, 509 priv->has_bwadj); 510 break; 511 case HCLK_EMMC: 512 case HCLK_SDMMC: 513 case HCLK_SDIO: 514 case SCLK_EMMC: 515 case SCLK_SDMMC: 516 case SCLK_SDIO: 517 new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, 518 clk->id, rate); 519 break; 520 case SCLK_SPI0: 521 case SCLK_SPI1: 522 new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ, 523 clk->id, rate); 524 break; 525 default: 526 return -ENOENT; 527 } 528 529 return new_rate; 530 } 531 532 static struct clk_ops rk3188_clk_ops = { 533 .get_rate = rk3188_clk_get_rate, 534 .set_rate = rk3188_clk_set_rate, 535 }; 536 537 static int rk3188_clk_ofdata_to_platdata(struct udevice *dev) 538 { 539 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 540 struct rk3188_clk_priv *priv = dev_get_priv(dev); 541 542 priv->cru = dev_read_addr_ptr(dev); 543 #endif 544 545 return 0; 546 } 547 548 static int rk3188_clk_probe(struct udevice *dev) 549 { 550 struct rk3188_clk_priv *priv = dev_get_priv(dev); 551 enum rk3188_clk_type type = dev_get_driver_data(dev); 552 553 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 554 if (IS_ERR(priv->grf)) 555 return PTR_ERR(priv->grf); 556 priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; 557 558 #ifdef CONFIG_SPL_BUILD 559 #if CONFIG_IS_ENABLED(OF_PLATDATA) 560 struct rk3188_clk_plat *plat = dev_get_platdata(dev); 561 562 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 563 #endif 564 565 rkclk_init(priv->cru, priv->grf, priv->has_bwadj); 566 #endif 567 568 return 0; 569 } 570 571 static int rk3188_clk_bind(struct udevice *dev) 572 { 573 int ret; 574 struct udevice *sys_child; 575 struct sysreset_reg *priv; 576 577 /* The reset driver does not have a device node, so bind it here */ 578 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 579 &sys_child); 580 if (ret) { 581 debug("Warning: No sysreset driver: ret=%d\n", ret); 582 } else { 583 priv = malloc(sizeof(struct sysreset_reg)); 584 priv->glb_srst_fst_value = offsetof(struct rk3188_cru, 585 cru_glb_srst_fst_value); 586 priv->glb_srst_snd_value = offsetof(struct rk3188_cru, 587 cru_glb_srst_snd_value); 588 sys_child->priv = priv; 589 } 590 591 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) 592 ret = offsetof(struct rk3188_cru, cru_softrst_con[0]); 593 ret = rockchip_reset_bind(dev, ret, 9); 594 if (ret) 595 debug("Warning: software reset driver bind faile\n"); 596 #endif 597 598 return 0; 599 } 600 601 static const struct udevice_id rk3188_clk_ids[] = { 602 { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU }, 603 { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU }, 604 { } 605 }; 606 607 U_BOOT_DRIVER(rockchip_rk3188_cru) = { 608 .name = "rockchip_rk3188_cru", 609 .id = UCLASS_CLK, 610 .of_match = rk3188_clk_ids, 611 .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv), 612 .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat), 613 .ops = &rk3188_clk_ops, 614 .bind = rk3188_clk_bind, 615 .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata, 616 .probe = rk3188_clk_probe, 617 }; 618