1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 /* Tegra30 Clock control functions */
8
9 #include <common.h>
10 #include <errno.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
16 #include <div64.h>
17 #include <fdtdec.h>
18
19 /*
20 * Clock types that we can use as a source. The Tegra30 has muxes for the
21 * peripheral clocks, and in most cases there are four options for the clock
22 * source. This gives us a clock 'type' and exploits what commonality exists
23 * in the device.
24 *
25 * Letters are obvious, except for T which means CLK_M, and S which means the
26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
27 * datasheet) and PLL_M are different things. The former is the basic
28 * clock supplied to the SOC from an external oscillator. The latter is the
29 * memory clock PLL.
30 *
31 * See definitions in clock_id in the header file.
32 */
33 enum clock_type_id {
34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
35 CLOCK_TYPE_MCPA, /* and so on */
36 CLOCK_TYPE_MCPT,
37 CLOCK_TYPE_PCM,
38 CLOCK_TYPE_PCMT,
39 CLOCK_TYPE_PCMT16,
40 CLOCK_TYPE_PDCT,
41 CLOCK_TYPE_ACPT,
42 CLOCK_TYPE_ASPTE,
43 CLOCK_TYPE_PMDACD2T,
44 CLOCK_TYPE_PCST,
45
46 CLOCK_TYPE_COUNT,
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
48 };
49
50 enum {
51 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
52 };
53
54 /*
55 * Clock source mux for each clock type. This just converts our enum into
56 * a list of mux sources for use by the code.
57 *
58 * Note:
59 * The extra column in each clock source array is used to store the mask
60 * bits in its register for the source.
61 */
62 #define CLK(x) CLOCK_ID_ ## x
63 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
65 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
66 MASK_BITS_31_30},
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
69 MASK_BITS_31_30},
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
72 MASK_BITS_31_30},
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
75 MASK_BITS_31_30},
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
78 MASK_BITS_31_30},
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 MASK_BITS_31_30},
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 MASK_BITS_31_30},
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 MASK_BITS_31_30},
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
89 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
90 MASK_BITS_31_29},
91 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
93 MASK_BITS_31_29},
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
96 MASK_BITS_31_28}
97 };
98
99 /*
100 * Clock type for each peripheral clock source. We put the name in each
101 * record just so it is easy to match things up
102 */
103 #define TYPE(name, type) type
104 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
105 /* 0x00 */
106 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
107 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
108 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
109 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
110 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
111 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
112 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
113 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
114
115 /* 0x08 */
116 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
117 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
118 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
119 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
120 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
121 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
122 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
123 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
124
125 /* 0x10 */
126 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
127 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
128 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
130 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
131 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
132 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
133 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
134
135 /* 0x18 */
136 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
137 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
138 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
139 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
140 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
141 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
142 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
143 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
144
145 /* 0x20 */
146 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
147 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
148 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
149 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
150 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
151 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
152 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
153 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
154
155 /* 0x28 */
156 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
157 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
158 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
159 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
161 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
162 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
163 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
164
165 /* 0x30 */
166 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
167 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
168 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
169 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
170 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
173 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
174
175 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
176 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
177 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
179 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
180 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
181 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
182 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
183 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
184
185 /* 0x40 */
186 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
187 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
188 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
189 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
190 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
191 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
192 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
193 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
194
195 /* 0x48 */
196 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
197 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
198 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
199 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
200 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
201 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
203 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
204
205 /* 0x50 */
206 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
211 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
213 };
214
215 /*
216 * This array translates a periph_id to a periphc_internal_id
217 *
218 * Not present/matched up:
219 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
220 * SPDIF - which is both 0x08 and 0x0c
221 *
222 */
223 #define NONE(name) (-1)
224 #define OFFSET(name, value) PERIPHC_ ## name
225 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
226 /* Low word: 31:0 */
227 NONE(CPU),
228 NONE(COP),
229 NONE(TRIGSYS),
230 NONE(RESERVED3),
231 NONE(RESERVED4),
232 NONE(TMR),
233 PERIPHC_UART1,
234 PERIPHC_UART2, /* and vfir 0x68 */
235
236 /* 8 */
237 NONE(GPIO),
238 PERIPHC_SDMMC2,
239 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
240 PERIPHC_I2S1,
241 PERIPHC_I2C1,
242 PERIPHC_NDFLASH,
243 PERIPHC_SDMMC1,
244 PERIPHC_SDMMC4,
245
246 /* 16 */
247 NONE(RESERVED16),
248 PERIPHC_PWM,
249 PERIPHC_I2S2,
250 PERIPHC_EPP,
251 PERIPHC_VI,
252 PERIPHC_G2D,
253 NONE(USBD),
254 NONE(ISP),
255
256 /* 24 */
257 PERIPHC_G3D,
258 NONE(RESERVED25),
259 PERIPHC_DISP2,
260 PERIPHC_DISP1,
261 PERIPHC_HOST1X,
262 NONE(VCP),
263 PERIPHC_I2S0,
264 NONE(CACHE2),
265
266 /* Middle word: 63:32 */
267 NONE(MEM),
268 NONE(AHBDMA),
269 NONE(APBDMA),
270 NONE(RESERVED35),
271 NONE(RESERVED36),
272 NONE(STAT_MON),
273 NONE(RESERVED38),
274 NONE(RESERVED39),
275
276 /* 40 */
277 NONE(KFUSE),
278 PERIPHC_SBC1,
279 PERIPHC_NOR,
280 NONE(RESERVED43),
281 PERIPHC_SBC2,
282 NONE(RESERVED45),
283 PERIPHC_SBC3,
284 PERIPHC_DVC_I2C,
285
286 /* 48 */
287 NONE(DSI),
288 PERIPHC_TVO, /* also CVE 0x40 */
289 PERIPHC_MIPI,
290 PERIPHC_HDMI,
291 NONE(CSI),
292 PERIPHC_TVDAC,
293 PERIPHC_I2C2,
294 PERIPHC_UART3,
295
296 /* 56 */
297 NONE(RESERVED56),
298 PERIPHC_EMC,
299 NONE(USB2),
300 NONE(USB3),
301 PERIPHC_MPE,
302 PERIPHC_VDE,
303 NONE(BSEA),
304 NONE(BSEV),
305
306 /* Upper word 95:64 */
307 PERIPHC_SPEEDO,
308 PERIPHC_UART4,
309 PERIPHC_UART5,
310 PERIPHC_I2C3,
311 PERIPHC_SBC4,
312 PERIPHC_SDMMC3,
313 NONE(PCIE),
314 PERIPHC_OWR,
315
316 /* 72 */
317 NONE(AFI),
318 PERIPHC_CSITE,
319 NONE(PCIEXCLK),
320 NONE(AVPUCQ),
321 NONE(RESERVED76),
322 NONE(RESERVED77),
323 NONE(RESERVED78),
324 NONE(DTV),
325
326 /* 80 */
327 PERIPHC_NANDSPEED,
328 PERIPHC_I2CSLOW,
329 NONE(DSIB),
330 NONE(RESERVED83),
331 NONE(IRAMA),
332 NONE(IRAMB),
333 NONE(IRAMC),
334 NONE(IRAMD),
335
336 /* 88 */
337 NONE(CRAM2),
338 NONE(RESERVED89),
339 NONE(MDOUBLER),
340 NONE(RESERVED91),
341 NONE(SUSOUT),
342 NONE(RESERVED93),
343 NONE(RESERVED94),
344 NONE(RESERVED95),
345
346 /* V word: 31:0 */
347 NONE(CPUG),
348 NONE(CPULP),
349 PERIPHC_G3D2,
350 PERIPHC_MSELECT,
351 PERIPHC_TSENSOR,
352 PERIPHC_I2S3,
353 PERIPHC_I2S4,
354 PERIPHC_I2C4,
355
356 /* 08 */
357 PERIPHC_SBC5,
358 PERIPHC_SBC6,
359 PERIPHC_AUDIO,
360 NONE(APBIF),
361 PERIPHC_DAM0,
362 PERIPHC_DAM1,
363 PERIPHC_DAM2,
364 PERIPHC_HDA2CODEC2X,
365
366 /* 16 */
367 NONE(ATOMICS),
368 NONE(RESERVED17),
369 NONE(RESERVED18),
370 NONE(RESERVED19),
371 NONE(RESERVED20),
372 NONE(RESERVED21),
373 NONE(RESERVED22),
374 PERIPHC_ACTMON,
375
376 /* 24 */
377 NONE(RESERVED24),
378 NONE(RESERVED25),
379 NONE(RESERVED26),
380 NONE(RESERVED27),
381 PERIPHC_SATA,
382 PERIPHC_HDA,
383 NONE(RESERVED30),
384 NONE(RESERVED31),
385
386 /* W word: 31:0 */
387 NONE(HDA2HDMICODEC),
388 NONE(SATACOLD),
389 NONE(RESERVED0_PCIERX0),
390 NONE(RESERVED1_PCIERX1),
391 NONE(RESERVED2_PCIERX2),
392 NONE(RESERVED3_PCIERX3),
393 NONE(RESERVED4_PCIERX4),
394 NONE(RESERVED5_PCIERX5),
395
396 /* 40 */
397 NONE(CEC),
398 NONE(RESERVED6_PCIE2),
399 NONE(RESERVED7_EMC),
400 NONE(RESERVED8_HDMI),
401 NONE(RESERVED9_SATA),
402 NONE(RESERVED10_MIPI),
403 NONE(EX_RESERVED46),
404 NONE(EX_RESERVED47),
405 };
406
407 /*
408 * PLL divider shift/mask tables for all PLL IDs.
409 */
410 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
411 /*
412 * T30: some deviations from T2x.
413 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
414 * If lock_ena or lock_det are >31, they're not used in that PLL.
415 */
416
417 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
418 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
419 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
420 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
421 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
422 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
423 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
424 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
425 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
426 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
427 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
428 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
429 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
430 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
431 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
432 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
433 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
434 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
435 };
436
437 /*
438 * Get the oscillator frequency, from the corresponding hardware configuration
439 * field. Note that T30 supports 3 new higher freqs, but we map back
440 * to the old T20 freqs. Support for the higher oscillators is TBD.
441 */
clock_get_osc_freq(void)442 enum clock_osc_freq clock_get_osc_freq(void)
443 {
444 struct clk_rst_ctlr *clkrst =
445 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
446 u32 reg;
447
448 reg = readl(&clkrst->crc_osc_ctrl);
449 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
450
451 if (reg & 1) /* one of the newer freqs */
452 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
453
454 return reg >> 2; /* Map to most common (T20) freqs */
455 }
456
457 /* Returns a pointer to the clock source register for a peripheral */
get_periph_source_reg(enum periph_id periph_id)458 u32 *get_periph_source_reg(enum periph_id periph_id)
459 {
460 struct clk_rst_ctlr *clkrst =
461 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
462 enum periphc_internal_id internal_id;
463
464 /* Coresight is a special case */
465 if (periph_id == PERIPH_ID_CSI)
466 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
467
468 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
469 internal_id = periph_id_to_internal_id[periph_id];
470 assert(internal_id != -1);
471 if (internal_id >= PERIPHC_VW_FIRST) {
472 internal_id -= PERIPHC_VW_FIRST;
473 return &clkrst->crc_clk_src_vw[internal_id];
474 } else
475 return &clkrst->crc_clk_src[internal_id];
476 }
477
get_periph_clock_info(enum periph_id periph_id,int * mux_bits,int * divider_bits,int * type)478 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
479 int *divider_bits, int *type)
480 {
481 enum periphc_internal_id internal_id;
482
483 if (!clock_periph_id_isvalid(periph_id))
484 return -1;
485
486 internal_id = periph_id_to_internal_id[periph_id];
487 if (!periphc_internal_id_isvalid(internal_id))
488 return -1;
489
490 *type = clock_periph_type[internal_id];
491 if (!clock_type_id_isvalid(*type))
492 return -1;
493
494 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
495
496 if (*type == CLOCK_TYPE_PCMT16)
497 *divider_bits = 16;
498 else
499 *divider_bits = 8;
500
501 return 0;
502 }
503
get_periph_clock_id(enum periph_id periph_id,int source)504 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
505 {
506 enum periphc_internal_id internal_id;
507 int type;
508
509 if (!clock_periph_id_isvalid(periph_id))
510 return CLOCK_ID_NONE;
511
512 internal_id = periph_id_to_internal_id[periph_id];
513 if (!periphc_internal_id_isvalid(internal_id))
514 return CLOCK_ID_NONE;
515
516 type = clock_periph_type[internal_id];
517 if (!clock_type_id_isvalid(type))
518 return CLOCK_ID_NONE;
519
520 return clock_source[type][source];
521 }
522
523 /**
524 * Given a peripheral ID and the required source clock, this returns which
525 * value should be programmed into the source mux for that peripheral.
526 *
527 * There is special code here to handle the one source type with 5 sources.
528 *
529 * @param periph_id peripheral to start
530 * @param source PLL id of required parent clock
531 * @param mux_bits Set to number of bits in mux register: 2 or 4
532 * @param divider_bits Set to number of divider bits (8 or 16)
533 * @return mux value (0-4, or -1 if not found)
534 */
get_periph_clock_source(enum periph_id periph_id,enum clock_id parent,int * mux_bits,int * divider_bits)535 int get_periph_clock_source(enum periph_id periph_id,
536 enum clock_id parent, int *mux_bits, int *divider_bits)
537 {
538 enum clock_type_id type;
539 int mux, err;
540
541 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
542 assert(!err);
543
544 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
545 if (clock_source[type][mux] == parent)
546 return mux;
547
548 /* if we get here, either us or the caller has made a mistake */
549 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
550 parent);
551 return -1;
552 }
553
clock_set_enable(enum periph_id periph_id,int enable)554 void clock_set_enable(enum periph_id periph_id, int enable)
555 {
556 struct clk_rst_ctlr *clkrst =
557 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
558 u32 *clk;
559 u32 reg;
560
561 /* Enable/disable the clock to this peripheral */
562 assert(clock_periph_id_isvalid(periph_id));
563 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
564 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
565 else
566 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
567 reg = readl(clk);
568 if (enable)
569 reg |= PERIPH_MASK(periph_id);
570 else
571 reg &= ~PERIPH_MASK(periph_id);
572 writel(reg, clk);
573 }
574
reset_set_enable(enum periph_id periph_id,int enable)575 void reset_set_enable(enum periph_id periph_id, int enable)
576 {
577 struct clk_rst_ctlr *clkrst =
578 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
579 u32 *reset;
580 u32 reg;
581
582 /* Enable/disable reset to the peripheral */
583 assert(clock_periph_id_isvalid(periph_id));
584 if (periph_id < PERIPH_ID_VW_FIRST)
585 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
586 else
587 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
588 reg = readl(reset);
589 if (enable)
590 reg |= PERIPH_MASK(periph_id);
591 else
592 reg &= ~PERIPH_MASK(periph_id);
593 writel(reg, reset);
594 }
595
596 #if CONFIG_IS_ENABLED(OF_CONTROL)
597 /*
598 * Convert a device tree clock ID to our peripheral ID. They are mostly
599 * the same but we are very cautious so we check that a valid clock ID is
600 * provided.
601 *
602 * @param clk_id Clock ID according to tegra30 device tree binding
603 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
604 */
clk_id_to_periph_id(int clk_id)605 enum periph_id clk_id_to_periph_id(int clk_id)
606 {
607 if (clk_id > PERIPH_ID_COUNT)
608 return PERIPH_ID_NONE;
609
610 switch (clk_id) {
611 case PERIPH_ID_RESERVED3:
612 case PERIPH_ID_RESERVED4:
613 case PERIPH_ID_RESERVED16:
614 case PERIPH_ID_RESERVED24:
615 case PERIPH_ID_RESERVED35:
616 case PERIPH_ID_RESERVED43:
617 case PERIPH_ID_RESERVED45:
618 case PERIPH_ID_RESERVED56:
619 case PERIPH_ID_PCIEXCLK:
620 case PERIPH_ID_RESERVED76:
621 case PERIPH_ID_RESERVED77:
622 case PERIPH_ID_RESERVED78:
623 case PERIPH_ID_RESERVED83:
624 case PERIPH_ID_RESERVED89:
625 case PERIPH_ID_RESERVED91:
626 case PERIPH_ID_RESERVED93:
627 case PERIPH_ID_RESERVED94:
628 case PERIPH_ID_RESERVED95:
629 return PERIPH_ID_NONE;
630 default:
631 return clk_id;
632 }
633 }
634 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
635
clock_early_init(void)636 void clock_early_init(void)
637 {
638 tegra30_set_up_pllp();
639 }
640
arch_timer_init(void)641 void arch_timer_init(void)
642 {
643 }
644
645 #define PMC_SATA_PWRGT 0x1ac
646 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
647 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
648
649 #define PLLE_SS_CNTL 0x68
650 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
651 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
652 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
653 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
654 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
655 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
656
657 #define PLLE_BASE 0x0e8
658 #define PLLE_BASE_ENABLE_CML (1 << 31)
659 #define PLLE_BASE_ENABLE (1 << 30)
660 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
661 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
662 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
664
665 #define PLLE_MISC 0x0ec
666 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
667 #define PLLE_MISC_PLL_READY (1 << 15)
668 #define PLLE_MISC_LOCK (1 << 11)
669 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
670 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
671
tegra_plle_train(void)672 static int tegra_plle_train(void)
673 {
674 unsigned int timeout = 2000;
675 unsigned long value;
676
677 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
678 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
679 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
680
681 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
682 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
683 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
684
685 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
686 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
687 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
688
689 do {
690 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
691 if (value & PLLE_MISC_PLL_READY)
692 break;
693
694 udelay(100);
695 } while (--timeout);
696
697 if (timeout == 0) {
698 pr_err("timeout waiting for PLLE to become ready");
699 return -ETIMEDOUT;
700 }
701
702 return 0;
703 }
704
tegra_plle_enable(void)705 int tegra_plle_enable(void)
706 {
707 unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
708 u32 value;
709 int err;
710
711 /* disable PLLE clock */
712 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
713 value &= ~PLLE_BASE_ENABLE_CML;
714 value &= ~PLLE_BASE_ENABLE;
715 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
716
717 /* clear lock enable and setup field */
718 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
719 value &= ~PLLE_MISC_LOCK_ENABLE;
720 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
721 value &= ~PLLE_MISC_SETUP_EXT(0x3);
722 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
723
724 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
725 if ((value & PLLE_MISC_PLL_READY) == 0) {
726 err = tegra_plle_train();
727 if (err < 0) {
728 pr_err("failed to train PLLE: %d", err);
729 return err;
730 }
731 }
732
733 /* configure PLLE */
734 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
735
736 value &= ~PLLE_BASE_PLDIV_CML(0x0f);
737 value |= PLLE_BASE_PLDIV_CML(cpcon);
738
739 value &= ~PLLE_BASE_PLDIV(0x3f);
740 value |= PLLE_BASE_PLDIV(p);
741
742 value &= ~PLLE_BASE_NDIV(0xff);
743 value |= PLLE_BASE_NDIV(n);
744
745 value &= ~PLLE_BASE_MDIV(0xff);
746 value |= PLLE_BASE_MDIV(m);
747
748 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
749
750 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
751 value |= PLLE_MISC_SETUP_BASE(0x7);
752 value |= PLLE_MISC_LOCK_ENABLE;
753 value |= PLLE_MISC_SETUP_EXT(0);
754 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
755
756 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
757 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
758 PLLE_SS_CNTL_BYPASS_SS;
759 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
760
761 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
762 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
763 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
764
765 do {
766 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
767 if (value & PLLE_MISC_LOCK)
768 break;
769
770 udelay(2);
771 } while (--timeout);
772
773 if (timeout == 0) {
774 pr_err("timeout waiting for PLLE to lock");
775 return -ETIMEDOUT;
776 }
777
778 udelay(50);
779
780 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
781 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
782 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
783
784 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
785 value |= PLLE_SS_CNTL_SSCINC(0x01);
786
787 value &= ~PLLE_SS_CNTL_SSCBYP;
788 value &= ~PLLE_SS_CNTL_INTERP_RESET;
789 value &= ~PLLE_SS_CNTL_BYPASS_SS;
790
791 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
792 value |= PLLE_SS_CNTL_SSCMAX(0x24);
793 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
794
795 return 0;
796 }
797
798 struct periph_clk_init periph_clk_init_table[] = {
799 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
800 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
801 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
802 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
803 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
804 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
805 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
806 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
807 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
808 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
809 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
810 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
811 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
812 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
813 { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
814 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
815 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
816 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
817 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
818 { -1, },
819 };
820