1 /* 2 * (C) Copyright 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 * 7 * Adapted from the very similar rk3288 ddr init. 8 */ 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <dt-structs.h> 14 #include <errno.h> 15 #include <ram.h> 16 #include <regmap.h> 17 #include <syscon.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/cru_rk3188.h> 21 #include <asm/arch/ddr_rk3188.h> 22 #include <asm/arch/grf_rk3188.h> 23 #include <asm/arch/pmu_rk3188.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/sdram_common.h> 26 #include <linux/err.h> 27 28 struct chan_info { 29 struct rk3288_ddr_pctl *pctl; 30 struct rk3288_ddr_publ *publ; 31 struct rk3188_msch *msch; 32 }; 33 34 struct dram_info { 35 struct chan_info chan[1]; 36 struct ram_info info; 37 struct clk ddr_clk; 38 struct rk3188_cru *cru; 39 struct rk3188_grf *grf; 40 struct rk3188_sgrf *sgrf; 41 struct rk3188_pmu *pmu; 42 }; 43 44 struct rk3188_sdram_params { 45 #if CONFIG_IS_ENABLED(OF_PLATDATA) 46 struct dtd_rockchip_rk3188_dmc of_plat; 47 #endif 48 struct rk3288_sdram_channel ch[2]; 49 struct rk3288_sdram_pctl_timing pctl_timing; 50 struct rk3288_sdram_phy_timing phy_timing; 51 struct rk3288_base_params base; 52 int num_channels; 53 struct regmap *map; 54 }; 55 56 const int ddrconf_table[] = { 57 /* 58 * [5:4] row(13+n) 59 * [1:0] col(9+n), assume bw=2 60 * row col,bw 61 */ 62 0, 63 ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 64 ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 65 ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 66 ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), 67 ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), 68 ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), 69 ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), 70 ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), 71 0, 72 0, 73 0, 74 0, 75 0, 76 0, 77 0, 78 }; 79 80 #define TEST_PATTEN 0x5aa5f00f 81 #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) 82 #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) 83 84 #ifdef CONFIG_SPL_BUILD 85 static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 86 { 87 int i; 88 89 for (i = 0; i < n / sizeof(u32); i++) { 90 writel(*src, dest); 91 src++; 92 dest++; 93 } 94 } 95 96 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) 97 { 98 u32 phy_ctl_srstn_shift = 13; 99 u32 ctl_psrstn_shift = 11; 100 u32 ctl_srstn_shift = 10; 101 u32 phy_psrstn_shift = 9; 102 u32 phy_srstn_shift = 8; 103 104 rk_clrsetreg(&cru->cru_softrst_con[5], 105 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | 106 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | 107 1 << phy_srstn_shift, 108 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | 109 ctl << ctl_srstn_shift | phy << phy_psrstn_shift | 110 phy << phy_srstn_shift); 111 } 112 113 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n) 114 { 115 u32 phy_ctl_srstn_shift = 13; 116 117 rk_clrsetreg(&cru->cru_softrst_con[5], 118 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); 119 } 120 121 static void phy_pctrl_reset(struct rk3188_cru *cru, 122 struct rk3288_ddr_publ *publ, 123 int channel) 124 { 125 int i; 126 127 ddr_reset(cru, channel, 1, 1); 128 udelay(1); 129 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); 130 for (i = 0; i < 4; i++) 131 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); 132 133 udelay(10); 134 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); 135 for (i = 0; i < 4; i++) 136 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); 137 138 udelay(10); 139 ddr_reset(cru, channel, 1, 0); 140 udelay(10); 141 ddr_reset(cru, channel, 0, 0); 142 udelay(10); 143 } 144 145 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, 146 u32 freq) 147 { 148 int i; 149 150 if (freq <= 250000000) { 151 if (freq <= 150000000) 152 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); 153 else 154 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); 155 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); 156 for (i = 0; i < 4; i++) 157 setbits_le32(&publ->datx8[i].dxdllcr, 158 DXDLLCR_DLLDIS); 159 160 setbits_le32(&publ->pir, PIR_DLLBYP); 161 } else { 162 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); 163 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); 164 for (i = 0; i < 4; i++) { 165 clrbits_le32(&publ->datx8[i].dxdllcr, 166 DXDLLCR_DLLDIS); 167 } 168 169 clrbits_le32(&publ->pir, PIR_DLLBYP); 170 } 171 } 172 173 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) 174 { 175 writel(DFI_INIT_START, &pctl->dfistcfg0); 176 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, 177 &pctl->dfistcfg1); 178 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 179 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 180 &pctl->dfilpcfg0); 181 182 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); 183 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); 184 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); 185 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); 186 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); 187 writel(1, &pctl->dfitphyupdtype0); 188 189 /* cs0 and cs1 write odt enable */ 190 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), 191 &pctl->dfiodtcfg); 192 /* odt write length */ 193 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 194 /* phyupd and ctrlupd disabled */ 195 writel(0, &pctl->dfiupdcfg); 196 } 197 198 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) 199 { 200 uint val = 0; 201 202 if (enable) 203 val = 1 << DDR_16BIT_EN_SHIFT; 204 205 rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); 206 } 207 208 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, 209 bool ddr3_mode) 210 { 211 uint mask, val; 212 213 mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; 214 val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; 215 rk_clrsetreg(&grf->soc_con2, mask, val); 216 } 217 218 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable) 219 { 220 uint mask, val; 221 222 mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; 223 val = enable << RANK_TO_ROW15_EN_SHIFT; 224 rk_clrsetreg(&grf->soc_con2, mask, val); 225 } 226 227 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, 228 struct rk3188_sdram_params *sdram_params, 229 struct rk3188_grf *grf) 230 { 231 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, 232 sizeof(sdram_params->pctl_timing)); 233 switch (sdram_params->base.dramtype) { 234 case DDR3: 235 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { 236 writel(sdram_params->pctl_timing.tcl - 3, 237 &pctl->dfitrddataen); 238 } else { 239 writel(sdram_params->pctl_timing.tcl - 2, 240 &pctl->dfitrddataen); 241 } 242 writel(sdram_params->pctl_timing.tcwl - 1, 243 &pctl->dfitphywrlat); 244 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | 245 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | 246 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, 247 &pctl->mcfg); 248 ddr_set_ddr3_mode(grf, channel, true); 249 ddr_set_enable(grf, channel, true); 250 break; 251 } 252 253 setbits_le32(&pctl->scfg, 1); 254 } 255 256 static void phy_cfg(const struct chan_info *chan, int channel, 257 struct rk3188_sdram_params *sdram_params) 258 { 259 struct rk3288_ddr_publ *publ = chan->publ; 260 struct rk3188_msch *msch = chan->msch; 261 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; 262 u32 dinit2; 263 int i; 264 265 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); 266 /* DDR PHY Timing */ 267 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, 268 sizeof(sdram_params->phy_timing)); 269 writel(sdram_params->base.noc_timing, &msch->ddrtiming); 270 writel(0x3f, &msch->readlatency); 271 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | 272 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | 273 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); 274 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | 275 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, 276 &publ->ptr[1]); 277 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | 278 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, 279 &publ->ptr[2]); 280 281 switch (sdram_params->base.dramtype) { 282 case DDR3: 283 clrbits_le32(&publ->pgcr, 0x1f); 284 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, 285 DDRMD_DDR3 << DDRMD_SHIFT); 286 break; 287 } 288 if (sdram_params->base.odt) { 289 /*dynamic RTT enable */ 290 for (i = 0; i < 4; i++) 291 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); 292 } else { 293 /*dynamic RTT disable */ 294 for (i = 0; i < 4; i++) 295 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); 296 } 297 } 298 299 static void phy_init(struct rk3288_ddr_publ *publ) 300 { 301 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST 302 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); 303 udelay(1); 304 while ((readl(&publ->pgsr) & 305 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != 306 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) 307 ; 308 } 309 310 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, 311 u32 cmd, u32 arg) 312 { 313 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); 314 udelay(1); 315 while (readl(&pctl->mcmd) & START_CMD) 316 ; 317 } 318 319 static inline void send_command_op(struct rk3288_ddr_pctl *pctl, 320 u32 rank, u32 cmd, u32 ma, u32 op) 321 { 322 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | 323 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); 324 } 325 326 static void memory_init(struct rk3288_ddr_publ *publ, 327 u32 dramtype) 328 { 329 setbits_le32(&publ->pir, 330 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP 331 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC 332 | (dramtype == DDR3 ? PIR_DRAMRST : 0))); 333 udelay(1); 334 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) 335 != (PGSR_IDONE | PGSR_DLDONE)) 336 ; 337 } 338 339 static void move_to_config_state(struct rk3288_ddr_publ *publ, 340 struct rk3288_ddr_pctl *pctl) 341 { 342 unsigned int state; 343 344 while (1) { 345 state = readl(&pctl->stat) & PCTL_STAT_MSK; 346 347 switch (state) { 348 case LOW_POWER: 349 writel(WAKEUP_STATE, &pctl->sctl); 350 while ((readl(&pctl->stat) & PCTL_STAT_MSK) 351 != ACCESS) 352 ; 353 /* wait DLL lock */ 354 while ((readl(&publ->pgsr) & PGSR_DLDONE) 355 != PGSR_DLDONE) 356 ; 357 /* 358 * if at low power state,need wakeup first, 359 * and then enter the config, so 360 * fallthrough 361 */ 362 case ACCESS: 363 /* fallthrough */ 364 case INIT_MEM: 365 writel(CFG_STATE, &pctl->sctl); 366 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 367 ; 368 break; 369 case CONFIG: 370 return; 371 default: 372 break; 373 } 374 } 375 } 376 377 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, 378 u32 n, struct rk3188_grf *grf) 379 { 380 struct rk3288_ddr_pctl *pctl = chan->pctl; 381 struct rk3288_ddr_publ *publ = chan->publ; 382 struct rk3188_msch *msch = chan->msch; 383 384 if (n == 1) { 385 setbits_le32(&pctl->ppcfg, 1); 386 ddr_set_enable(grf, channel, 1); 387 setbits_le32(&msch->ddrtiming, 1 << 31); 388 /* Data Byte disable*/ 389 clrbits_le32(&publ->datx8[2].dxgcr, 1); 390 clrbits_le32(&publ->datx8[3].dxgcr, 1); 391 /* disable DLL */ 392 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); 393 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); 394 } else { 395 clrbits_le32(&pctl->ppcfg, 1); 396 ddr_set_enable(grf, channel, 0); 397 clrbits_le32(&msch->ddrtiming, 1 << 31); 398 /* Data Byte enable*/ 399 setbits_le32(&publ->datx8[2].dxgcr, 1); 400 setbits_le32(&publ->datx8[3].dxgcr, 1); 401 402 /* enable DLL */ 403 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); 404 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); 405 /* reset DLL */ 406 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); 407 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); 408 udelay(10); 409 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); 410 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); 411 } 412 setbits_le32(&pctl->dfistcfg0, 1 << 2); 413 } 414 415 static int data_training(const struct chan_info *chan, int channel, 416 struct rk3188_sdram_params *sdram_params) 417 { 418 unsigned int j; 419 int ret = 0; 420 u32 rank; 421 int i; 422 u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; 423 struct rk3288_ddr_publ *publ = chan->publ; 424 struct rk3288_ddr_pctl *pctl = chan->pctl; 425 426 /* disable auto refresh */ 427 writel(0, &pctl->trefi); 428 429 if (sdram_params->base.dramtype != LPDDR3) 430 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); 431 rank = sdram_params->ch[channel].rank | 1; 432 for (j = 0; j < ARRAY_SIZE(step); j++) { 433 /* 434 * trigger QSTRN and RVTRN 435 * clear DTDONE status 436 */ 437 setbits_le32(&publ->pir, PIR_CLRSR); 438 439 /* trigger DTT */ 440 setbits_le32(&publ->pir, 441 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | 442 PIR_CLRSR); 443 udelay(1); 444 /* wait echo byte DTDONE */ 445 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) 446 != rank) 447 ; 448 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) 449 != rank) 450 ; 451 if (!(readl(&pctl->ppcfg) & 1)) { 452 while ((readl(&publ->datx8[2].dxgsr[0]) 453 & rank) != rank) 454 ; 455 while ((readl(&publ->datx8[3].dxgsr[0]) 456 & rank) != rank) 457 ; 458 } 459 if (readl(&publ->pgsr) & 460 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { 461 ret = -1; 462 break; 463 } 464 } 465 /* send some auto refresh to complement the lost while DTT */ 466 for (i = 0; i < (rank > 1 ? 8 : 4); i++) 467 send_command(pctl, rank, REF_CMD, 0); 468 469 if (sdram_params->base.dramtype != LPDDR3) 470 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); 471 472 /* resume auto refresh */ 473 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); 474 475 return ret; 476 } 477 478 static void move_to_access_state(const struct chan_info *chan) 479 { 480 struct rk3288_ddr_publ *publ = chan->publ; 481 struct rk3288_ddr_pctl *pctl = chan->pctl; 482 unsigned int state; 483 484 while (1) { 485 state = readl(&pctl->stat) & PCTL_STAT_MSK; 486 487 switch (state) { 488 case LOW_POWER: 489 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & 490 LP_TRIG_MASK) == 1) 491 return; 492 493 writel(WAKEUP_STATE, &pctl->sctl); 494 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 495 ; 496 /* wait DLL lock */ 497 while ((readl(&publ->pgsr) & PGSR_DLDONE) 498 != PGSR_DLDONE) 499 ; 500 break; 501 case INIT_MEM: 502 writel(CFG_STATE, &pctl->sctl); 503 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 504 ; 505 /* fallthrough */ 506 case CONFIG: 507 writel(GO_STATE, &pctl->sctl); 508 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) 509 ; 510 break; 511 case ACCESS: 512 return; 513 default: 514 break; 515 } 516 } 517 } 518 519 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, 520 struct rk3188_sdram_params *sdram_params) 521 { 522 struct rk3288_ddr_publ *publ = chan->publ; 523 524 if (sdram_params->ch[chnum].bk == 3) 525 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, 526 1 << PDQ_SHIFT); 527 else 528 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); 529 530 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); 531 } 532 533 static void dram_all_config(const struct dram_info *dram, 534 struct rk3188_sdram_params *sdram_params) 535 { 536 unsigned int chan; 537 u32 sys_reg = 0; 538 539 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; 540 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; 541 for (chan = 0; chan < sdram_params->num_channels; chan++) { 542 const struct rk3288_sdram_channel *info = 543 &sdram_params->ch[chan]; 544 545 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); 546 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); 547 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); 548 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); 549 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); 550 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); 551 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); 552 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); 553 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); 554 555 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); 556 } 557 if (sdram_params->ch[0].rank == 2) 558 ddr_rank_2_row15en(dram->grf, 0); 559 else 560 ddr_rank_2_row15en(dram->grf, 1); 561 562 writel(sys_reg, &dram->pmu->sys_reg[2]); 563 } 564 565 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, 566 struct rk3188_sdram_params *sdram_params) 567 { 568 int reg; 569 int need_trainig = 0; 570 const struct chan_info *chan = &dram->chan[channel]; 571 struct rk3288_ddr_publ *publ = chan->publ; 572 573 ddr_rank_2_row15en(dram->grf, 0); 574 575 if (data_training(chan, channel, sdram_params) < 0) { 576 printf("first data training fail!\n"); 577 reg = readl(&publ->datx8[0].dxgsr[0]); 578 /* Check the result for rank 0 */ 579 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { 580 printf("data training fail!\n"); 581 return -EIO; 582 } 583 584 /* Check the result for rank 1 */ 585 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { 586 sdram_params->ch[channel].rank = 1; 587 clrsetbits_le32(&publ->pgcr, 0xF << 18, 588 sdram_params->ch[channel].rank << 18); 589 need_trainig = 1; 590 } 591 reg = readl(&publ->datx8[2].dxgsr[0]); 592 if (reg & (1 << 4)) { 593 sdram_params->ch[channel].bw = 1; 594 set_bandwidth_ratio(chan, channel, 595 sdram_params->ch[channel].bw, 596 dram->grf); 597 need_trainig = 1; 598 } 599 } 600 /* Assume the Die bit width are the same with the chip bit width */ 601 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; 602 603 if (need_trainig && 604 (data_training(chan, channel, sdram_params) < 0)) { 605 if (sdram_params->base.dramtype == LPDDR3) { 606 ddr_phy_ctl_reset(dram->cru, channel, 1); 607 udelay(10); 608 ddr_phy_ctl_reset(dram->cru, channel, 0); 609 udelay(10); 610 } 611 printf("2nd data training failed!"); 612 return -EIO; 613 } 614 615 return 0; 616 } 617 618 /* 619 * Detect ram columns and rows. 620 * @dram: dram info struct 621 * @channel: channel number to handle 622 * @sdram_params: sdram parameters, function will fill in col and row values 623 * 624 * Returns 0 or negative on error. 625 */ 626 static int sdram_col_row_detect(struct dram_info *dram, int channel, 627 struct rk3188_sdram_params *sdram_params) 628 { 629 int row, col; 630 unsigned int addr; 631 const struct chan_info *chan = &dram->chan[channel]; 632 struct rk3288_ddr_pctl *pctl = chan->pctl; 633 struct rk3288_ddr_publ *publ = chan->publ; 634 int ret = 0; 635 636 /* Detect col */ 637 for (col = 11; col >= 9; col--) { 638 writel(0, CONFIG_SYS_SDRAM_BASE); 639 addr = CONFIG_SYS_SDRAM_BASE + 640 (1 << (col + sdram_params->ch[channel].bw - 1)); 641 writel(TEST_PATTEN, addr); 642 if ((readl(addr) == TEST_PATTEN) && 643 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 644 break; 645 } 646 if (col == 8) { 647 printf("Col detect error\n"); 648 ret = -EINVAL; 649 goto out; 650 } else { 651 sdram_params->ch[channel].col = col; 652 } 653 654 ddr_rank_2_row15en(dram->grf, 1); 655 move_to_config_state(publ, pctl); 656 writel(1, &chan->msch->ddrconf); 657 move_to_access_state(chan); 658 /* Detect row, max 15,min13 in rk3188*/ 659 for (row = 16; row >= 13; row--) { 660 writel(0, CONFIG_SYS_SDRAM_BASE); 661 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); 662 writel(TEST_PATTEN, addr); 663 if ((readl(addr) == TEST_PATTEN) && 664 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 665 break; 666 } 667 if (row == 12) { 668 printf("Row detect error\n"); 669 ret = -EINVAL; 670 } else { 671 sdram_params->ch[channel].cs1_row = row; 672 sdram_params->ch[channel].row_3_4 = 0; 673 debug("chn %d col %d, row %d\n", channel, col, row); 674 sdram_params->ch[channel].cs0_row = row; 675 } 676 677 out: 678 return ret; 679 } 680 681 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) 682 { 683 int i, tmp, size, row, ret = 0; 684 685 row = sdram_params->ch[0].cs0_row; 686 /* 687 * RK3188 share the rank and row bit15, we use same ddr config for 15bit 688 * and 16bit row 689 */ 690 if (row == 16) 691 row = 15; 692 tmp = sdram_params->ch[0].col - 9; 693 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; 694 tmp |= ((row - 13) << 4); 695 size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); 696 for (i = 0; i < size; i++) 697 if (tmp == ddrconf_table[i]) 698 break; 699 if (i >= size) { 700 printf("niu config not found\n"); 701 ret = -EINVAL; 702 } else { 703 debug("niu config %d\n", i); 704 sdram_params->base.ddrconfig = i; 705 } 706 707 return ret; 708 } 709 710 static int sdram_init(struct dram_info *dram, 711 struct rk3188_sdram_params *sdram_params) 712 { 713 int channel; 714 int zqcr; 715 int ret; 716 717 if ((sdram_params->base.dramtype == DDR3 && 718 sdram_params->base.ddr_freq > 800000000)) { 719 printf("SDRAM frequency is too high!"); 720 return -E2BIG; 721 } 722 723 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); 724 if (ret) { 725 printf("Could not set DDR clock\n"); 726 return ret; 727 } 728 729 for (channel = 0; channel < 1; channel++) { 730 const struct chan_info *chan = &dram->chan[channel]; 731 struct rk3288_ddr_pctl *pctl = chan->pctl; 732 struct rk3288_ddr_publ *publ = chan->publ; 733 734 phy_pctrl_reset(dram->cru, publ, channel); 735 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); 736 737 dfi_cfg(pctl, sdram_params->base.dramtype); 738 739 pctl_cfg(channel, pctl, sdram_params, dram->grf); 740 741 phy_cfg(chan, channel, sdram_params); 742 743 phy_init(publ); 744 745 writel(POWER_UP_START, &pctl->powctl); 746 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) 747 ; 748 749 memory_init(publ, sdram_params->base.dramtype); 750 move_to_config_state(publ, pctl); 751 752 /* Using 32bit bus width for detect */ 753 sdram_params->ch[channel].bw = 2; 754 set_bandwidth_ratio(chan, channel, 755 sdram_params->ch[channel].bw, dram->grf); 756 /* 757 * set cs, using n=3 for detect 758 * CS0, n=1 759 * CS1, n=2 760 * CS0 & CS1, n = 3 761 */ 762 sdram_params->ch[channel].rank = 2, 763 clrsetbits_le32(&publ->pgcr, 0xF << 18, 764 (sdram_params->ch[channel].rank | 1) << 18); 765 766 /* DS=40ohm,ODT=155ohm */ 767 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | 768 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | 769 0x19 << PD_OUTPUT_SHIFT; 770 writel(zqcr, &publ->zq1cr[0]); 771 writel(zqcr, &publ->zq0cr[0]); 772 773 /* Detect the rank and bit-width with data-training */ 774 writel(1, &chan->msch->ddrconf); 775 sdram_rank_bw_detect(dram, channel, sdram_params); 776 777 if (sdram_params->base.dramtype == LPDDR3) { 778 u32 i; 779 writel(0, &pctl->mrrcfg0); 780 for (i = 0; i < 17; i++) 781 send_command_op(pctl, 1, MRR_CMD, i, 0); 782 } 783 writel(4, &chan->msch->ddrconf); 784 move_to_access_state(chan); 785 /* DDR3 and LPDDR3 are always 8 bank, no need detect */ 786 sdram_params->ch[channel].bk = 3; 787 /* Detect Col and Row number*/ 788 ret = sdram_col_row_detect(dram, channel, sdram_params); 789 if (ret) 790 goto error; 791 } 792 /* Find NIU DDR configuration */ 793 ret = sdram_get_niu_config(sdram_params); 794 if (ret) 795 goto error; 796 797 dram_all_config(dram, sdram_params); 798 debug("%s done\n", __func__); 799 800 return 0; 801 error: 802 printf("DRAM init failed!\n"); 803 hang(); 804 } 805 806 static int setup_sdram(struct udevice *dev) 807 { 808 struct dram_info *priv = dev_get_priv(dev); 809 struct rk3188_sdram_params *params = dev_get_platdata(dev); 810 811 return sdram_init(priv, params); 812 } 813 814 static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev) 815 { 816 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 817 struct rk3188_sdram_params *params = dev_get_platdata(dev); 818 int ret; 819 820 /* rk3188 supports only one-channel */ 821 params->num_channels = 1; 822 ret = dev_read_u32_array(dev, "rockchip,pctl-timing", 823 (u32 *)¶ms->pctl_timing, 824 sizeof(params->pctl_timing) / sizeof(u32)); 825 if (ret) { 826 printf("%s: Cannot read rockchip,pctl-timing\n", __func__); 827 return -EINVAL; 828 } 829 ret = dev_read_u32_array(dev, "rockchip,phy-timing", 830 (u32 *)¶ms->phy_timing, 831 sizeof(params->phy_timing) / sizeof(u32)); 832 if (ret) { 833 printf("%s: Cannot read rockchip,phy-timing\n", __func__); 834 return -EINVAL; 835 } 836 ret = dev_read_u32_array(dev, "rockchip,sdram-params", 837 (u32 *)¶ms->base, 838 sizeof(params->base) / sizeof(u32)); 839 if (ret) { 840 printf("%s: Cannot read rockchip,sdram-params\n", __func__); 841 return -EINVAL; 842 } 843 ret = regmap_init_mem(dev, ¶ms->map); 844 if (ret) 845 return ret; 846 #endif 847 848 return 0; 849 } 850 #endif /* CONFIG_SPL_BUILD */ 851 852 #if CONFIG_IS_ENABLED(OF_PLATDATA) 853 static int conv_of_platdata(struct udevice *dev) 854 { 855 struct rk3188_sdram_params *plat = dev_get_platdata(dev); 856 struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat; 857 int ret; 858 859 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, 860 sizeof(plat->pctl_timing)); 861 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, 862 sizeof(plat->phy_timing)); 863 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); 864 /* rk3188 supports dual-channel, set default channel num to 2 */ 865 plat->num_channels = 1; 866 ret = regmap_init_mem_platdata(dev, of_plat->reg, 867 ARRAY_SIZE(of_plat->reg) / 2, 868 &plat->map); 869 if (ret) 870 return ret; 871 872 return 0; 873 } 874 #endif 875 876 static int rk3188_dmc_probe(struct udevice *dev) 877 { 878 #ifdef CONFIG_SPL_BUILD 879 struct rk3188_sdram_params *plat = dev_get_platdata(dev); 880 struct regmap *map; 881 struct udevice *dev_clk; 882 int ret; 883 #endif 884 struct dram_info *priv = dev_get_priv(dev); 885 886 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 887 888 #ifdef CONFIG_SPL_BUILD 889 #if CONFIG_IS_ENABLED(OF_PLATDATA) 890 ret = conv_of_platdata(dev); 891 if (ret) 892 return ret; 893 #endif 894 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); 895 if (IS_ERR(map)) 896 return PTR_ERR(map); 897 priv->chan[0].msch = regmap_get_range(map, 0); 898 899 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 900 901 priv->chan[0].pctl = regmap_get_range(plat->map, 0); 902 priv->chan[0].publ = regmap_get_range(plat->map, 1); 903 904 ret = rockchip_get_clk(&dev_clk); 905 if (ret) 906 return ret; 907 priv->ddr_clk.id = CLK_DDR; 908 ret = clk_request(dev_clk, &priv->ddr_clk); 909 if (ret) 910 return ret; 911 912 priv->cru = rockchip_get_cru(); 913 if (IS_ERR(priv->cru)) 914 return PTR_ERR(priv->cru); 915 ret = setup_sdram(dev); 916 if (ret) 917 return ret; 918 #else 919 priv->info.base = CONFIG_SYS_SDRAM_BASE; 920 priv->info.size = rockchip_sdram_size( 921 (phys_addr_t)&priv->pmu->sys_reg[2]); 922 #endif 923 924 return 0; 925 } 926 927 static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info) 928 { 929 struct dram_info *priv = dev_get_priv(dev); 930 931 *info = priv->info; 932 933 return 0; 934 } 935 936 static struct ram_ops rk3188_dmc_ops = { 937 .get_info = rk3188_dmc_get_info, 938 }; 939 940 static const struct udevice_id rk3188_dmc_ids[] = { 941 { .compatible = "rockchip,rk3188-dmc" }, 942 { } 943 }; 944 945 U_BOOT_DRIVER(dmc_rk3188) = { 946 .name = "rockchip_rk3188_dmc", 947 .id = UCLASS_RAM, 948 .of_match = rk3188_dmc_ids, 949 .ops = &rk3188_dmc_ops, 950 #ifdef CONFIG_SPL_BUILD 951 .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata, 952 #endif 953 .probe = rk3188_dmc_probe, 954 .priv_auto_alloc_size = sizeof(struct dram_info), 955 #ifdef CONFIG_SPL_BUILD 956 .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params), 957 #endif 958 }; 959