1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * (C) Copyright 2009 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <div64.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/sys_proto.h> 16 17 /* General purpose timers registers */ 18 struct mxc_gpt { 19 unsigned int control; 20 unsigned int prescaler; 21 unsigned int status; 22 unsigned int nouse[6]; 23 unsigned int counter; 24 }; 25 26 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; 27 28 /* General purpose timers bitfields */ 29 #define GPTCR_SWR (1 << 15) /* Software reset */ 30 #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */ 31 #define GPTCR_FRR (1 << 9) /* Freerun / restart */ 32 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ 33 #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ 34 #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ 35 #define GPTCR_CLKSOURCE_MASK (0x7 << 6) 36 #define GPTCR_TEN 1 /* Timer enable */ 37 38 #define GPTPR_PRESCALER24M_SHIFT 12 39 #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT) 40 41 static inline int gpt_has_clk_source_osc(void) 42 { 43 #if defined(CONFIG_MX6) 44 if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || 45 is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || 46 is_mx6ull() || is_mx6sll()) 47 return 1; 48 49 return 0; 50 #else 51 return 0; 52 #endif 53 } 54 55 static inline ulong gpt_get_clk(void) 56 { 57 #ifdef CONFIG_MXC_GPT_HCLK 58 if (gpt_has_clk_source_osc()) 59 return MXC_HCLK >> 3; 60 else 61 return mxc_get_clock(MXC_IPG_PERCLK); 62 #else 63 return MXC_CLK32; 64 #endif 65 } 66 67 int timer_init(void) 68 { 69 int i; 70 71 /* setup GP Timer 1 */ 72 __raw_writel(GPTCR_SWR, &cur_gpt->control); 73 74 /* We have no udelay by now */ 75 __raw_writel(0, &cur_gpt->control); 76 77 i = __raw_readl(&cur_gpt->control); 78 i &= ~GPTCR_CLKSOURCE_MASK; 79 80 #ifdef CONFIG_MXC_GPT_HCLK 81 if (gpt_has_clk_source_osc()) { 82 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; 83 84 /* 85 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC 86 * Enable bit and prescaler 87 */ 88 if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() || 89 is_mx6sll()) { 90 i |= GPTCR_24MEN; 91 92 /* Produce 3Mhz clock */ 93 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), 94 &cur_gpt->prescaler); 95 } 96 } else { 97 i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN; 98 } 99 #else 100 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ 101 i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; 102 #endif 103 __raw_writel(i, &cur_gpt->control); 104 105 return 0; 106 } 107 108 unsigned long timer_read_counter(void) 109 { 110 return __raw_readl(&cur_gpt->counter); /* current tick value */ 111 } 112 113 /* 114 * This function is derived from PowerPC code (timebase clock frequency). 115 * On ARM it returns the number of timer ticks per second. 116 */ 117 ulong get_tbclk(void) 118 { 119 return gpt_get_clk(); 120 } 121 122 /* 123 * This function is intended for SHORT delays only. 124 * It will overflow at around 10 seconds @ 400MHz, 125 * or 20 seconds @ 200MHz. 126 */ 127 unsigned long usec2ticks(unsigned long _usec) 128 { 129 unsigned long long usec = _usec; 130 131 usec *= get_tbclk(); 132 usec += 999999; 133 do_div(usec, 1000000); 134 135 return usec; 136 } 137