1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/mmu.h> 10 #include <asm/io.h> 11 #include <common.h> 12 #include <mpc83xx.h> 13 #include <pci.h> 14 #include <i2c.h> 15 #include <asm/fsl_i2c.h> 16 17 static struct pci_region pci1_regions[] = { 18 { 19 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 20 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 21 size: CONFIG_SYS_PCI1_MEM_SIZE, 22 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 23 }, 24 { 25 bus_start: CONFIG_SYS_PCI1_IO_BASE, 26 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 27 size: CONFIG_SYS_PCI1_IO_SIZE, 28 flags: PCI_REGION_IO 29 }, 30 { 31 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 32 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 33 size: CONFIG_SYS_PCI1_MMIO_SIZE, 34 flags: PCI_REGION_MEM 35 }, 36 }; 37 38 /* 39 * pci_init_board() 40 * 41 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since 42 * per TQM834x design physical connections to external devices (PCI sockets) 43 * are routed only to the PCI1 we do not account for the second one - this code 44 * supports PCI1 module only. Should support for the PCI2 be required in the 45 * future it needs a separate pci_controller structure (above) and handling - 46 * please refer to other boards' implementation for dual PCI host controllers, 47 * for example board/Marvell/db64360/pci.c, pci_init_board() 48 * 49 */ 50 void 51 pci_init_board(void) 52 { 53 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 54 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 55 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 56 struct pci_region *reg[] = { pci1_regions }; 57 u32 reg32; 58 59 /* 60 * Configure PCI controller and PCI_CLK_OUTPUT 61 * 62 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one 63 * line actually used for clocking all external PCI devices in TQM83xx. 64 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 65 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 66 * are known to hang the board; this issue is under investigation 67 * (13 oct 05) 68 */ 69 reg32 = OCCR_PCICOE1; 70 #if 0 71 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ 72 reg32 = 0xff000000; 73 #endif 74 if (clk->spmr & SPMR_CKID) { 75 /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR 76 * fields accordingly */ 77 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); 78 79 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ 80 | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ 81 | OCCR_PCICD6 | OCCR_PCICD7); 82 } 83 84 clk->occr = reg32; 85 udelay(2000); 86 87 /* Configure PCI Local Access Windows */ 88 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 89 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 90 91 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 92 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; 93 94 udelay(2000); 95 96 mpc83xx_pci_init(1, reg); 97 } 98