1 /* 2 * spi driver for rockchip 3 * 4 * (C) Copyright 2015 Google, Inc 5 * 6 * (C) Copyright 2008-2013 Rockchip Electronics 7 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <dt-structs.h> 16 #include <errno.h> 17 #include <spi.h> 18 #include <linux/errno.h> 19 #include <asm/io.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/periph.h> 22 #include <dm/pinctrl.h> 23 #include "rk_spi.h" 24 25 /* Change to 1 to output registers at the start of each transaction */ 26 #define DEBUG_RK_SPI 0 27 28 struct rockchip_spi_platdata { 29 #if CONFIG_IS_ENABLED(OF_PLATDATA) 30 struct dtd_rockchip_rk3288_spi of_plat; 31 #endif 32 s32 frequency; /* Default clock frequency, -1 for none */ 33 fdt_addr_t base; 34 uint deactivate_delay_us; /* Delay to wait after deactivate */ 35 uint activate_delay_us; /* Delay to wait after activate */ 36 }; 37 38 struct rockchip_spi_priv { 39 struct rockchip_spi *regs; 40 struct clk clk; 41 unsigned int max_freq; 42 unsigned int mode; 43 ulong last_transaction_us; /* Time of last transaction end */ 44 u8 bits_per_word; /* max 16 bits per word */ 45 u8 n_bytes; 46 unsigned int speed_hz; 47 unsigned int last_speed_hz; 48 unsigned int tmode; 49 uint input_rate; 50 }; 51 52 #define SPI_FIFO_DEPTH 32 53 54 static void rkspi_dump_regs(struct rockchip_spi *regs) 55 { 56 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); 57 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); 58 debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); 59 debug("ser: \t\t0x%08x\n", readl(®s->ser)); 60 debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); 61 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); 62 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); 63 debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); 64 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); 65 debug("sr: \t\t0x%08x\n", readl(®s->sr)); 66 debug("imr: \t\t0x%08x\n", readl(®s->imr)); 67 debug("isr: \t\t0x%08x\n", readl(®s->isr)); 68 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); 69 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); 70 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); 71 } 72 73 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) 74 { 75 writel(enable ? 1 : 0, ®s->enr); 76 } 77 78 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) 79 { 80 /* 81 * We should try not to exceed the speed requested by the caller: 82 * when selecting a divider, we need to make sure we round up. 83 */ 84 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); 85 86 /* The baudrate register (BAUDR) is defined as a 32bit register where 87 * the upper 16bit are reserved and having 'Fsclk_out' in the lower 88 * 16bits with 'Fsclk_out' defined as follows: 89 * 90 * Fsclk_out = Fspi_clk/ SCKDV 91 * Where SCKDV is any even value between 2 and 65534. 92 */ 93 if (clk_div > 0xfffe) { 94 clk_div = 0xfffe; 95 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n", 96 __func__, speed, priv->input_rate / clk_div); 97 } 98 99 /* Round up to the next even 16bit number */ 100 clk_div = (clk_div + 1) & 0xfffe; 101 102 debug("spi speed %u, div %u\n", speed, clk_div); 103 104 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); 105 priv->last_speed_hz = speed; 106 } 107 108 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) 109 { 110 unsigned long start; 111 112 start = get_timer(0); 113 while (readl(®s->sr) & SR_BUSY) { 114 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) { 115 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); 116 return -ETIMEDOUT; 117 } 118 } 119 120 return 0; 121 } 122 123 static void spi_cs_activate(struct udevice *dev, uint cs) 124 { 125 struct udevice *bus = dev->parent; 126 struct rockchip_spi_platdata *plat = bus->platdata; 127 struct rockchip_spi_priv *priv = dev_get_priv(bus); 128 struct rockchip_spi *regs = priv->regs; 129 130 /* If it's too soon to do another transaction, wait */ 131 if (plat->deactivate_delay_us && priv->last_transaction_us) { 132 ulong delay_us; /* The delay completed so far */ 133 delay_us = timer_get_us() - priv->last_transaction_us; 134 if (delay_us < plat->deactivate_delay_us) 135 udelay(plat->deactivate_delay_us - delay_us); 136 } 137 138 debug("activate cs%u\n", cs); 139 writel(1 << cs, ®s->ser); 140 if (plat->activate_delay_us) 141 udelay(plat->activate_delay_us); 142 } 143 144 static void spi_cs_deactivate(struct udevice *dev, uint cs) 145 { 146 struct udevice *bus = dev->parent; 147 struct rockchip_spi_platdata *plat = bus->platdata; 148 struct rockchip_spi_priv *priv = dev_get_priv(bus); 149 struct rockchip_spi *regs = priv->regs; 150 151 debug("deactivate cs%u\n", cs); 152 writel(0, ®s->ser); 153 154 /* Remember time of this transaction so we can honour the bus delay */ 155 if (plat->deactivate_delay_us) 156 priv->last_transaction_us = timer_get_us(); 157 } 158 159 #if CONFIG_IS_ENABLED(OF_PLATDATA) 160 static int conv_of_platdata(struct udevice *dev) 161 { 162 struct rockchip_spi_platdata *plat = dev->platdata; 163 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; 164 struct rockchip_spi_priv *priv = dev_get_priv(dev); 165 int ret; 166 167 plat->base = dtplat->reg[0]; 168 plat->frequency = 20000000; 169 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); 170 if (ret < 0) 171 return ret; 172 dev->req_seq = 0; 173 174 return 0; 175 } 176 #endif 177 178 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) 179 { 180 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 181 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 182 struct rockchip_spi_priv *priv = dev_get_priv(bus); 183 int ret; 184 185 plat->base = dev_read_addr(bus); 186 187 ret = clk_get_by_index(bus, 0, &priv->clk); 188 if (ret < 0) { 189 debug("%s: Could not get clock for %s: %d\n", __func__, 190 bus->name, ret); 191 return ret; 192 } 193 194 plat->frequency = 195 dev_read_u32_default(bus, "spi-max-frequency", 50000000); 196 plat->deactivate_delay_us = 197 dev_read_u32_default(bus, "spi-deactivate-delay", 0); 198 plat->activate_delay_us = 199 dev_read_u32_default(bus, "spi-activate-delay", 0); 200 201 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", 202 __func__, (uint)plat->base, plat->frequency, 203 plat->deactivate_delay_us); 204 #endif 205 206 return 0; 207 } 208 209 static int rockchip_spi_calc_modclk(ulong max_freq) 210 { 211 /* 212 * While this is not strictly correct for the RK3368, as the 213 * GPLL will be 576MHz, things will still work, as the 214 * clk_set_rate(...) implementation in our clock-driver will 215 * chose the next closest rate not exceeding what we request 216 * based on the output of this function. 217 */ 218 219 unsigned div; 220 const unsigned long gpll_hz = 594000000UL; 221 222 /* 223 * We need to find an input clock that provides at least twice 224 * the maximum frequency and can be generated from the assumed 225 * speed of GPLL (594MHz) using an integer divider. 226 * 227 * To give us more achievable bitrates at higher speeds (these 228 * are generated by dividing by an even 16-bit integer from 229 * this frequency), we try to have an input frequency of at 230 * least 4x our max_freq. 231 */ 232 233 div = DIV_ROUND_UP(gpll_hz, max_freq * 4); 234 return gpll_hz / div; 235 } 236 237 static int rockchip_spi_probe(struct udevice *bus) 238 { 239 struct rockchip_spi_platdata *plat = dev_get_platdata(bus); 240 struct rockchip_spi_priv *priv = dev_get_priv(bus); 241 int ret; 242 243 debug("%s: probe\n", __func__); 244 #if CONFIG_IS_ENABLED(OF_PLATDATA) 245 ret = conv_of_platdata(bus); 246 if (ret) 247 return ret; 248 #endif 249 priv->regs = (struct rockchip_spi *)plat->base; 250 251 priv->last_transaction_us = timer_get_us(); 252 priv->max_freq = plat->frequency; 253 254 /* Clamp the value from the DTS against any hardware limits */ 255 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) 256 priv->max_freq = ROCKCHIP_SPI_MAX_RATE; 257 258 /* Find a module-input clock that fits with the max_freq setting */ 259 ret = clk_set_rate(&priv->clk, 260 rockchip_spi_calc_modclk(priv->max_freq)); 261 if (ret < 0) { 262 debug("%s: Failed to set clock: %d\n", __func__, ret); 263 return ret; 264 } 265 priv->input_rate = ret; 266 debug("%s: rate = %u\n", __func__, priv->input_rate); 267 priv->bits_per_word = 8; 268 priv->tmode = TMOD_TR; /* Tx & Rx */ 269 270 return 0; 271 } 272 273 static int rockchip_spi_claim_bus(struct udevice *dev) 274 { 275 struct udevice *bus = dev->parent; 276 struct rockchip_spi_priv *priv = dev_get_priv(bus); 277 struct rockchip_spi *regs = priv->regs; 278 u8 spi_dfs, spi_tf; 279 uint ctrlr0; 280 281 /* Disable the SPI hardware */ 282 rkspi_enable_chip(regs, 0); 283 284 switch (priv->bits_per_word) { 285 case 8: 286 priv->n_bytes = 1; 287 spi_dfs = DFS_8BIT; 288 spi_tf = HALF_WORD_OFF; 289 break; 290 case 16: 291 priv->n_bytes = 2; 292 spi_dfs = DFS_16BIT; 293 spi_tf = HALF_WORD_ON; 294 break; 295 default: 296 debug("%s: unsupported bits: %dbits\n", __func__, 297 priv->bits_per_word); 298 return -EPROTONOSUPPORT; 299 } 300 301 if (priv->speed_hz != priv->last_speed_hz) 302 rkspi_set_clk(priv, priv->speed_hz); 303 304 /* Operation Mode */ 305 ctrlr0 = OMOD_MASTER << OMOD_SHIFT; 306 307 /* Data Frame Size */ 308 ctrlr0 |= spi_dfs << DFS_SHIFT; 309 310 /* set SPI mode 0..3 */ 311 if (priv->mode & SPI_CPOL) 312 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT; 313 if (priv->mode & SPI_CPHA) 314 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT; 315 316 /* Chip Select Mode */ 317 ctrlr0 |= CSM_KEEP << CSM_SHIFT; 318 319 /* SSN to Sclk_out delay */ 320 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT; 321 322 /* Serial Endian Mode */ 323 ctrlr0 |= SEM_LITTLE << SEM_SHIFT; 324 325 /* First Bit Mode */ 326 ctrlr0 |= FBM_MSB << FBM_SHIFT; 327 328 /* Byte and Halfword Transform */ 329 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT; 330 331 /* Rxd Sample Delay */ 332 ctrlr0 |= 0 << RXDSD_SHIFT; 333 334 /* Frame Format */ 335 ctrlr0 |= FRF_SPI << FRF_SHIFT; 336 337 /* Tx and Rx mode */ 338 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; 339 340 writel(ctrlr0, ®s->ctrlr0); 341 342 return 0; 343 } 344 345 static int rockchip_spi_release_bus(struct udevice *dev) 346 { 347 struct udevice *bus = dev->parent; 348 struct rockchip_spi_priv *priv = dev_get_priv(bus); 349 350 rkspi_enable_chip(priv->regs, false); 351 352 return 0; 353 } 354 355 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, 356 const void *dout, void *din, unsigned long flags) 357 { 358 struct udevice *bus = dev->parent; 359 struct rockchip_spi_priv *priv = dev_get_priv(bus); 360 struct rockchip_spi *regs = priv->regs; 361 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 362 int len = bitlen >> 3; 363 const u8 *out = dout; 364 u8 *in = din; 365 int toread, towrite; 366 int ret; 367 368 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, 369 len, flags); 370 if (DEBUG_RK_SPI) 371 rkspi_dump_regs(regs); 372 373 /* Assert CS before transfer */ 374 if (flags & SPI_XFER_BEGIN) 375 spi_cs_activate(dev, slave_plat->cs); 376 377 while (len > 0) { 378 int todo = min(len, 0xffff); 379 380 rkspi_enable_chip(regs, false); 381 writel(todo - 1, ®s->ctrlr1); 382 rkspi_enable_chip(regs, true); 383 384 toread = todo; 385 towrite = todo; 386 while (toread || towrite) { 387 u32 status = readl(®s->sr); 388 389 if (towrite && !(status & SR_TF_FULL)) { 390 writel(out ? *out++ : 0, regs->txdr); 391 towrite--; 392 } 393 if (toread && !(status & SR_RF_EMPT)) { 394 u32 byte = readl(regs->rxdr); 395 396 if (in) 397 *in++ = byte; 398 toread--; 399 } 400 } 401 ret = rkspi_wait_till_not_busy(regs); 402 if (ret) 403 break; 404 len -= todo; 405 } 406 407 /* Deassert CS after transfer */ 408 if (flags & SPI_XFER_END) 409 spi_cs_deactivate(dev, slave_plat->cs); 410 411 rkspi_enable_chip(regs, false); 412 413 return ret; 414 } 415 416 static int rockchip_spi_set_speed(struct udevice *bus, uint speed) 417 { 418 struct rockchip_spi_priv *priv = dev_get_priv(bus); 419 420 /* Clamp to the maximum frequency specified in the DTS */ 421 if (speed > priv->max_freq) 422 speed = priv->max_freq; 423 424 priv->speed_hz = speed; 425 426 return 0; 427 } 428 429 static int rockchip_spi_set_mode(struct udevice *bus, uint mode) 430 { 431 struct rockchip_spi_priv *priv = dev_get_priv(bus); 432 433 priv->mode = mode; 434 435 return 0; 436 } 437 438 static const struct dm_spi_ops rockchip_spi_ops = { 439 .claim_bus = rockchip_spi_claim_bus, 440 .release_bus = rockchip_spi_release_bus, 441 .xfer = rockchip_spi_xfer, 442 .set_speed = rockchip_spi_set_speed, 443 .set_mode = rockchip_spi_set_mode, 444 /* 445 * cs_info is not needed, since we require all chip selects to be 446 * in the device tree explicitly 447 */ 448 }; 449 450 static const struct udevice_id rockchip_spi_ids[] = { 451 { .compatible = "rockchip,rk3288-spi" }, 452 { .compatible = "rockchip,rk3368-spi" }, 453 { .compatible = "rockchip,rk3399-spi" }, 454 { } 455 }; 456 457 U_BOOT_DRIVER(rockchip_spi) = { 458 #if CONFIG_IS_ENABLED(OF_PLATDATA) 459 .name = "rockchip_rk3288_spi", 460 #else 461 .name = "rockchip_spi", 462 #endif 463 .id = UCLASS_SPI, 464 .of_match = rockchip_spi_ids, 465 .ops = &rockchip_spi_ops, 466 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, 467 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata), 468 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv), 469 .probe = rockchip_spi_probe, 470 }; 471