1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. 3 * Copyright (c) 2010-2011 NVIDIA Corporation 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <i2c.h> 13 #include <asm/io.h> 14 #include <clk.h> 15 #include <reset.h> 16 #ifndef CONFIG_TEGRA186 17 #include <asm/arch/clock.h> 18 #include <asm/arch/funcmux.h> 19 #endif 20 #include <asm/arch/gpio.h> 21 #include <asm/arch-tegra/tegra_i2c.h> 22 23 enum i2c_type { 24 TYPE_114, 25 TYPE_STD, 26 TYPE_DVC, 27 }; 28 29 /* Information about i2c controller */ 30 struct i2c_bus { 31 int id; 32 struct reset_ctl reset_ctl; 33 struct clk clk; 34 int speed; 35 int pinmux_config; 36 struct i2c_control *control; 37 struct i2c_ctlr *regs; 38 enum i2c_type type; 39 int inited; /* bus is inited */ 40 }; 41 42 static void set_packet_mode(struct i2c_bus *i2c_bus) 43 { 44 u32 config; 45 46 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; 47 48 if (i2c_bus->type == TYPE_DVC) { 49 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 50 51 writel(config, &dvc->cnfg); 52 } else { 53 writel(config, &i2c_bus->regs->cnfg); 54 /* 55 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe 56 * issues, i.e., some slaves may be wrongly detected. 57 */ 58 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); 59 } 60 } 61 62 static void i2c_reset_controller(struct i2c_bus *i2c_bus) 63 { 64 /* Reset I2C controller. */ 65 reset_assert(&i2c_bus->reset_ctl); 66 udelay(1); 67 reset_deassert(&i2c_bus->reset_ctl); 68 udelay(1); 69 70 /* re-program config register to packet mode */ 71 set_packet_mode(i2c_bus); 72 } 73 74 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate) 75 { 76 int ret; 77 78 ret = reset_assert(&i2c_bus->reset_ctl); 79 if (ret) 80 return ret; 81 ret = clk_enable(&i2c_bus->clk); 82 if (ret) 83 return ret; 84 ret = clk_set_rate(&i2c_bus->clk, rate); 85 if (IS_ERR_VALUE(ret)) 86 return ret; 87 ret = reset_deassert(&i2c_bus->reset_ctl); 88 if (ret) 89 return ret; 90 91 return 0; 92 } 93 94 static void i2c_init_controller(struct i2c_bus *i2c_bus) 95 { 96 if (!i2c_bus->speed) 97 return; 98 debug("%s: speed=%d\n", __func__, i2c_bus->speed); 99 /* 100 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 101 * here, in section 23.3.1, but in fact we seem to need a factor of 102 * 16 to get the right frequency. 103 */ 104 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8); 105 106 if (i2c_bus->type == TYPE_114) { 107 /* 108 * T114 I2C went to a single clock source for standard/fast and 109 * HS clock speeds. The new clock rate setting calculation is: 110 * SCL = CLK_SOURCE.I2C / 111 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * 112 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). 113 * 114 * NOTE: We do this here, after the initial clock/pll start, 115 * because if we read the clk_div reg before the controller 116 * is running, we hang, and we need it for the new calc. 117 */ 118 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; 119 unsigned rate = CLK_MULT_STD_FAST_MODE * 120 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2; 121 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, 122 clk_div_stdfst_mode); 123 124 i2c_init_clock(i2c_bus, rate); 125 } 126 127 /* Reset I2C controller. */ 128 i2c_reset_controller(i2c_bus); 129 130 /* Configure I2C controller. */ 131 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */ 132 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 133 134 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); 135 } 136 137 #ifndef CONFIG_TEGRA186 138 funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config); 139 #endif 140 } 141 142 static void send_packet_headers( 143 struct i2c_bus *i2c_bus, 144 struct i2c_trans_info *trans, 145 u32 packet_id, 146 bool end_with_repeated_start) 147 { 148 u32 data; 149 150 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ 151 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; 152 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; 153 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; 154 writel(data, &i2c_bus->control->tx_fifo); 155 debug("pkt header 1 sent (0x%x)\n", data); 156 157 /* prepare header2 */ 158 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; 159 writel(data, &i2c_bus->control->tx_fifo); 160 debug("pkt header 2 sent (0x%x)\n", data); 161 162 /* prepare IO specific header: configure the slave address */ 163 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; 164 165 /* Enable Read if it is not a write transaction */ 166 if (!(trans->flags & I2C_IS_WRITE)) 167 data |= PKT_HDR3_READ_MODE_MASK; 168 if (end_with_repeated_start) 169 data |= PKT_HDR3_REPEAT_START_MASK; 170 171 /* Write I2C specific header */ 172 writel(data, &i2c_bus->control->tx_fifo); 173 debug("pkt header 3 sent (0x%x)\n", data); 174 } 175 176 static int wait_for_tx_fifo_empty(struct i2c_control *control) 177 { 178 u32 count; 179 int timeout_us = I2C_TIMEOUT_USEC; 180 181 while (timeout_us >= 0) { 182 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) 183 >> TX_FIFO_EMPTY_CNT_SHIFT; 184 if (count == I2C_FIFO_DEPTH) 185 return 1; 186 udelay(10); 187 timeout_us -= 10; 188 } 189 190 return 0; 191 } 192 193 static int wait_for_rx_fifo_notempty(struct i2c_control *control) 194 { 195 u32 count; 196 int timeout_us = I2C_TIMEOUT_USEC; 197 198 while (timeout_us >= 0) { 199 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) 200 >> TX_FIFO_FULL_CNT_SHIFT; 201 if (count) 202 return 1; 203 udelay(10); 204 timeout_us -= 10; 205 } 206 207 return 0; 208 } 209 210 static int wait_for_transfer_complete(struct i2c_control *control) 211 { 212 int int_status; 213 int timeout_us = I2C_TIMEOUT_USEC; 214 215 while (timeout_us >= 0) { 216 int_status = readl(&control->int_status); 217 if (int_status & I2C_INT_NO_ACK_MASK) 218 return -int_status; 219 if (int_status & I2C_INT_ARBITRATION_LOST_MASK) 220 return -int_status; 221 if (int_status & I2C_INT_XFER_COMPLETE_MASK) 222 return 0; 223 224 udelay(10); 225 timeout_us -= 10; 226 } 227 228 return -1; 229 } 230 231 static int send_recv_packets(struct i2c_bus *i2c_bus, 232 struct i2c_trans_info *trans) 233 { 234 struct i2c_control *control = i2c_bus->control; 235 u32 int_status; 236 u32 words; 237 u8 *dptr; 238 u32 local; 239 uchar last_bytes; 240 int error = 0; 241 int is_write = trans->flags & I2C_IS_WRITE; 242 243 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ 244 int_status = readl(&control->int_status); 245 writel(int_status, &control->int_status); 246 247 send_packet_headers(i2c_bus, trans, 1, 248 trans->flags & I2C_USE_REPEATED_START); 249 250 words = DIV_ROUND_UP(trans->num_bytes, 4); 251 last_bytes = trans->num_bytes & 3; 252 dptr = trans->buf; 253 254 while (words) { 255 u32 *wptr = (u32 *)dptr; 256 257 if (is_write) { 258 /* deal with word alignment */ 259 if ((words == 1) && last_bytes) { 260 local = 0; 261 memcpy(&local, dptr, last_bytes); 262 } else if ((unsigned long)dptr & 3) { 263 memcpy(&local, dptr, sizeof(u32)); 264 } else { 265 local = *wptr; 266 } 267 writel(local, &control->tx_fifo); 268 debug("pkt data sent (0x%x)\n", local); 269 if (!wait_for_tx_fifo_empty(control)) { 270 error = -1; 271 goto exit; 272 } 273 } else { 274 if (!wait_for_rx_fifo_notempty(control)) { 275 error = -1; 276 goto exit; 277 } 278 /* 279 * for the last word, we read into our local buffer, 280 * in case that caller did not provide enough buffer. 281 */ 282 local = readl(&control->rx_fifo); 283 if ((words == 1) && last_bytes) 284 memcpy(dptr, (char *)&local, last_bytes); 285 else if ((unsigned long)dptr & 3) 286 memcpy(dptr, &local, sizeof(u32)); 287 else 288 *wptr = local; 289 debug("pkt data received (0x%x)\n", local); 290 } 291 words--; 292 dptr += sizeof(u32); 293 } 294 295 if (wait_for_transfer_complete(control)) { 296 error = -1; 297 goto exit; 298 } 299 return 0; 300 exit: 301 /* error, reset the controller. */ 302 i2c_reset_controller(i2c_bus); 303 304 return error; 305 } 306 307 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, 308 u32 len, bool end_with_repeated_start) 309 { 310 int error; 311 struct i2c_trans_info trans_info; 312 313 trans_info.address = addr; 314 trans_info.buf = data; 315 trans_info.flags = I2C_IS_WRITE; 316 if (end_with_repeated_start) 317 trans_info.flags |= I2C_USE_REPEATED_START; 318 trans_info.num_bytes = len; 319 trans_info.is_10bit_address = 0; 320 321 error = send_recv_packets(i2c_bus, &trans_info); 322 if (error) 323 debug("tegra_i2c_write_data: Error (%d) !!!\n", error); 324 325 return error; 326 } 327 328 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, 329 u32 len) 330 { 331 int error; 332 struct i2c_trans_info trans_info; 333 334 trans_info.address = addr | 1; 335 trans_info.buf = data; 336 trans_info.flags = 0; 337 trans_info.num_bytes = len; 338 trans_info.is_10bit_address = 0; 339 340 error = send_recv_packets(i2c_bus, &trans_info); 341 if (error) 342 debug("tegra_i2c_read_data: Error (%d) !!!\n", error); 343 344 return error; 345 } 346 347 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 348 { 349 struct i2c_bus *i2c_bus = dev_get_priv(dev); 350 351 i2c_bus->speed = speed; 352 i2c_init_controller(i2c_bus); 353 354 return 0; 355 } 356 357 static int tegra_i2c_probe(struct udevice *dev) 358 { 359 struct i2c_bus *i2c_bus = dev_get_priv(dev); 360 int ret; 361 bool is_dvc; 362 363 i2c_bus->id = dev->seq; 364 i2c_bus->type = dev_get_driver_data(dev); 365 i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev); 366 if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) { 367 debug("%s: Cannot get regs address\n", __func__); 368 return -EINVAL; 369 } 370 371 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl); 372 if (ret) { 373 pr_err("reset_get_by_name() failed: %d\n", ret); 374 return ret; 375 } 376 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk); 377 if (ret) { 378 pr_err("clk_get_by_name() failed: %d\n", ret); 379 return ret; 380 } 381 382 #ifndef CONFIG_TEGRA186 383 /* 384 * We don't have a binding for pinmux yet. Leave it out for now. So 385 * far no one needs anything other than the default. 386 */ 387 i2c_bus->pinmux_config = FUNCMUX_DEFAULT; 388 389 /* 390 * We can't specify the pinmux config in the fdt, so I2C2 will not 391 * work on Seaboard. It normally has no devices on it anyway. 392 * You could add in this little hack if you need to use it. 393 * The correct solution is a pinmux binding in the fdt. 394 * 395 * if (i2c_bus->clk.id == PERIPH_ID_I2C2) 396 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; 397 */ 398 #endif 399 400 is_dvc = dev_get_driver_data(dev) == TYPE_DVC; 401 if (is_dvc) { 402 i2c_bus->control = 403 &((struct dvc_ctlr *)i2c_bus->regs)->control; 404 } else { 405 i2c_bus->control = &i2c_bus->regs->control; 406 } 407 i2c_init_controller(i2c_bus); 408 debug("%s: controller bus %d at %p, speed %d: ", 409 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed); 410 411 return 0; 412 } 413 414 /* i2c write version without the register address */ 415 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, 416 int len, bool end_with_repeated_start) 417 { 418 int rc; 419 420 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 421 debug("write_data: "); 422 /* use rc for counter */ 423 for (rc = 0; rc < len; ++rc) 424 debug(" 0x%02x", buffer[rc]); 425 debug("\n"); 426 427 /* Shift 7-bit address over for lower-level i2c functions */ 428 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len, 429 end_with_repeated_start); 430 if (rc) 431 debug("i2c_write_data(): rc=%d\n", rc); 432 433 return rc; 434 } 435 436 /* i2c read version without the register address */ 437 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, 438 int len) 439 { 440 int rc; 441 442 debug("inside i2c_read_data():\n"); 443 /* Shift 7-bit address over for lower-level i2c functions */ 444 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len); 445 if (rc) { 446 debug("i2c_read_data(): rc=%d\n", rc); 447 return rc; 448 } 449 450 debug("i2c_read_data: "); 451 /* reuse rc for counter*/ 452 for (rc = 0; rc < len; ++rc) 453 debug(" 0x%02x", buffer[rc]); 454 debug("\n"); 455 456 return 0; 457 } 458 459 /* Probe to see if a chip is present. */ 460 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr, 461 uint chip_flags) 462 { 463 struct i2c_bus *i2c_bus = dev_get_priv(bus); 464 int rc; 465 u8 reg; 466 467 /* Shift 7-bit address over for lower-level i2c functions */ 468 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg), 469 false); 470 471 return rc; 472 } 473 474 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 475 int nmsgs) 476 { 477 struct i2c_bus *i2c_bus = dev_get_priv(bus); 478 int ret; 479 480 debug("i2c_xfer: %d messages\n", nmsgs); 481 for (; nmsgs > 0; nmsgs--, msg++) { 482 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 483 484 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 485 if (msg->flags & I2C_M_RD) { 486 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, 487 msg->len); 488 } else { 489 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, 490 msg->len, next_is_read); 491 } 492 if (ret) { 493 debug("i2c_write: error sending\n"); 494 return -EREMOTEIO; 495 } 496 } 497 498 return 0; 499 } 500 501 int tegra_i2c_get_dvc_bus(struct udevice **busp) 502 { 503 struct udevice *bus; 504 505 for (uclass_first_device(UCLASS_I2C, &bus); 506 bus; 507 uclass_next_device(&bus)) { 508 if (dev_get_driver_data(bus) == TYPE_DVC) { 509 *busp = bus; 510 return 0; 511 } 512 } 513 514 return -ENODEV; 515 } 516 517 static const struct dm_i2c_ops tegra_i2c_ops = { 518 .xfer = tegra_i2c_xfer, 519 .probe_chip = tegra_i2c_probe_chip, 520 .set_bus_speed = tegra_i2c_set_bus_speed, 521 }; 522 523 static const struct udevice_id tegra_i2c_ids[] = { 524 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 }, 525 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD }, 526 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC }, 527 { } 528 }; 529 530 U_BOOT_DRIVER(i2c_tegra) = { 531 .name = "i2c_tegra", 532 .id = UCLASS_I2C, 533 .of_match = tegra_i2c_ids, 534 .probe = tegra_i2c_probe, 535 .priv_auto_alloc_size = sizeof(struct i2c_bus), 536 .ops = &tegra_i2c_ops, 537 }; 538