1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <hwconfig.h> 10 #include <i2c.h> 11 #include <spi.h> 12 #include <linux/libfdt.h> 13 #include <fdt_support.h> 14 #include <pci.h> 15 #include <mpc83xx.h> 16 #include <fsl_esdhc.h> 17 #include <asm/io.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_mpc83xx_serdes.h> 20 21 #include "mpc8308.h" 22 23 #include <gdsys_fpga.h> 24 25 #include "../common/adv7611.h" 26 #include "../common/ch7301.h" 27 #include "../common/dp501.h" 28 #include "../common/ioep-fpga.h" 29 #include "../common/mclink.h" 30 #include "../common/osd.h" 31 #include "../common/phy.h" 32 #include "../common/fanctrl.h" 33 34 #include <pca953x.h> 35 #include <pca9698.h> 36 37 #include <miiphy.h> 38 39 #define MAX_MUX_CHANNELS 2 40 41 enum { 42 MCFPGA_DONE = 1 << 0, 43 MCFPGA_INIT_N = 1 << 1, 44 MCFPGA_PROGRAM_N = 1 << 2, 45 MCFPGA_UPDATE_ENABLE_N = 1 << 3, 46 MCFPGA_RESET_N = 1 << 4, 47 }; 48 49 enum { 50 GPIO_MDC = 1 << 14, 51 GPIO_MDIO = 1 << 15, 52 }; 53 54 unsigned int mclink_fpgacount; 55 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; 56 57 struct { 58 u8 bus; 59 u8 addr; 60 } strider_fans[] = CONFIG_STRIDER_FANS; 61 62 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) 63 { 64 int res; 65 66 switch (fpga) { 67 case 0: 68 out_le16(reg, data); 69 break; 70 default: 71 res = mclink_send(fpga - 1, regoff, data); 72 if (res < 0) { 73 printf("mclink_send reg %02lx data %04x returned %d\n", 74 regoff, data, res); 75 return res; 76 } 77 break; 78 } 79 80 return 0; 81 } 82 83 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) 84 { 85 int res; 86 87 switch (fpga) { 88 case 0: 89 *data = in_le16(reg); 90 break; 91 default: 92 if (fpga > mclink_fpgacount) 93 return -EINVAL; 94 res = mclink_receive(fpga - 1, regoff, data); 95 if (res < 0) { 96 printf("mclink_receive reg %02lx returned %d\n", 97 regoff, res); 98 return res; 99 } 100 } 101 102 return 0; 103 } 104 105 int checkboard(void) 106 { 107 char *s = env_get("serial#"); 108 bool hw_type_cat = pca9698_get_value(0x20, 18); 109 110 puts("Board: "); 111 112 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); 113 114 if (s != NULL) { 115 puts(", serial# "); 116 puts(s); 117 } 118 119 puts("\n"); 120 121 return 0; 122 } 123 124 int last_stage_init(void) 125 { 126 int slaves; 127 unsigned int k; 128 unsigned int mux_ch; 129 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; 130 #ifdef CONFIG_STRIDER_CPU 131 unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; 132 #endif 133 bool hw_type_cat = pca9698_get_value(0x20, 18); 134 #ifdef CONFIG_STRIDER_CON_DP 135 bool is_dh = pca9698_get_value(0x20, 25); 136 #endif 137 bool ch0_sgmii2_present = false; 138 139 /* Turn on Analog Devices ADV7611 */ 140 pca9698_direction_output(0x20, 8, 0); 141 142 /* Turn on Parade DP501 */ 143 pca9698_direction_output(0x20, 10, 1); 144 pca9698_direction_output(0x20, 11, 1); 145 146 ch0_sgmii2_present = !pca9698_get_value(0x20, 37); 147 148 /* wait for FPGA done, then reset FPGA */ 149 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { 150 unsigned int ctr = 0; 151 unsigned char *mclink_controllers = mclink_controllers_dvi; 152 153 #ifdef CONFIG_STRIDER_CPU 154 if (i2c_probe(mclink_controllers[k])) { 155 mclink_controllers = mclink_controllers_dp; 156 if (i2c_probe(mclink_controllers[k])) 157 continue; 158 } 159 #else 160 if (i2c_probe(mclink_controllers[k])) 161 continue; 162 #endif 163 while (!(pca953x_get_val(mclink_controllers[k]) 164 & MCFPGA_DONE)) { 165 udelay(100000); 166 if (ctr++ > 5) { 167 printf("no done for mclink_controller %d\n", k); 168 break; 169 } 170 } 171 172 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); 173 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); 174 udelay(10); 175 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 176 MCFPGA_RESET_N); 177 } 178 179 if (hw_type_cat) { 180 int retval; 181 struct mii_dev *mdiodev = mdio_alloc(); 182 if (!mdiodev) 183 return -ENOMEM; 184 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); 185 mdiodev->read = bb_miiphy_read; 186 mdiodev->write = bb_miiphy_write; 187 188 retval = mdio_register(mdiodev); 189 if (retval < 0) 190 return retval; 191 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { 192 if ((mux_ch == 1) && !ch0_sgmii2_present) 193 continue; 194 195 setup_88e1514(bb_miiphy_buses[0].name, mux_ch); 196 } 197 } 198 199 /* give slave-PLLs and Parade DP501 some time to be up and running */ 200 udelay(500000); 201 202 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; 203 slaves = mclink_probe(); 204 mclink_fpgacount = 0; 205 206 ioep_fpga_print_info(0); 207 208 if (!adv7611_probe(0)) 209 printf(" Advantiv ADV7611 HDMI Receiver\n"); 210 211 #ifdef CONFIG_STRIDER_CON 212 if (ioep_fpga_has_osd(0)) 213 osd_probe(0); 214 #endif 215 216 #ifdef CONFIG_STRIDER_CON_DP 217 if (ioep_fpga_has_osd(0)) { 218 osd_probe(0); 219 if (is_dh) 220 osd_probe(4); 221 } 222 #endif 223 224 #ifdef CONFIG_STRIDER_CPU 225 ch7301_probe(0, false); 226 dp501_probe(0, false); 227 #endif 228 229 if (slaves <= 0) 230 return 0; 231 232 mclink_fpgacount = slaves; 233 234 #ifdef CONFIG_STRIDER_CPU 235 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */ 236 for (k = 1; k <= slaves; ++k) 237 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ 238 239 udelay(500000); 240 #endif 241 242 for (k = 1; k <= slaves; ++k) { 243 ioep_fpga_print_info(k); 244 #ifdef CONFIG_STRIDER_CON 245 if (ioep_fpga_has_osd(k)) 246 osd_probe(k); 247 #endif 248 #ifdef CONFIG_STRIDER_CON_DP 249 if (ioep_fpga_has_osd(k)) { 250 osd_probe(k); 251 if (is_dh) 252 osd_probe(k + 4); 253 } 254 #endif 255 #ifdef CONFIG_STRIDER_CPU 256 if (!adv7611_probe(k)) 257 printf(" Advantiv ADV7611 HDMI Receiver\n"); 258 ch7301_probe(k, false); 259 dp501_probe(k, false); 260 #endif 261 if (hw_type_cat) { 262 int retval; 263 struct mii_dev *mdiodev = mdio_alloc(); 264 if (!mdiodev) 265 return -ENOMEM; 266 strncpy(mdiodev->name, bb_miiphy_buses[k].name, 267 MDIO_NAME_LEN); 268 mdiodev->read = bb_miiphy_read; 269 mdiodev->write = bb_miiphy_write; 270 271 retval = mdio_register(mdiodev); 272 if (retval < 0) 273 return retval; 274 setup_88e1514(bb_miiphy_buses[k].name, 0); 275 } 276 } 277 278 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { 279 i2c_set_bus_num(strider_fans[k].bus); 280 init_fan_controller(strider_fans[k].addr); 281 } 282 283 return 0; 284 } 285 286 /* 287 * provide access to fpga gpios (for I2C bitbang) 288 * (these may look all too simple but make iocon.h much more readable) 289 */ 290 void fpga_gpio_set(unsigned int bus, int pin) 291 { 292 FPGA_SET_REG(bus, gpio.set, pin); 293 } 294 295 void fpga_gpio_clear(unsigned int bus, int pin) 296 { 297 FPGA_SET_REG(bus, gpio.clear, pin); 298 } 299 300 int fpga_gpio_get(unsigned int bus, int pin) 301 { 302 u16 val; 303 304 FPGA_GET_REG(bus, gpio.read, &val); 305 306 return val & pin; 307 } 308 309 #ifdef CONFIG_STRIDER_CON_DP 310 void fpga_control_set(unsigned int bus, int pin) 311 { 312 u16 val; 313 314 FPGA_GET_REG(bus, control, &val); 315 FPGA_SET_REG(bus, control, val | pin); 316 } 317 318 void fpga_control_clear(unsigned int bus, int pin) 319 { 320 u16 val; 321 322 FPGA_GET_REG(bus, control, &val); 323 FPGA_SET_REG(bus, control, val & ~pin); 324 } 325 #endif 326 327 void mpc8308_init(void) 328 { 329 pca9698_direction_output(0x20, 26, 1); 330 } 331 332 void mpc8308_set_fpga_reset(unsigned state) 333 { 334 pca9698_set_value(0x20, 26, state ? 0 : 1); 335 } 336 337 void mpc8308_setup_hw(void) 338 { 339 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 340 341 /* 342 * set "startup-finished"-gpios 343 */ 344 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); 345 setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); 346 } 347 348 int mpc8308_get_fpga_done(unsigned fpga) 349 { 350 return pca9698_get_value(0x20, 20); 351 } 352 353 #ifdef CONFIG_FSL_ESDHC 354 int board_mmc_init(bd_t *bd) 355 { 356 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 357 sysconf83xx_t *sysconf = &immr->sysconf; 358 359 /* Enable cache snooping in eSDHC system configuration register */ 360 out_be32(&sysconf->sdhccr, 0x02000000); 361 362 return fsl_esdhc_mmc_init(bd); 363 } 364 #endif 365 366 static struct pci_region pcie_regions_0[] = { 367 { 368 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 369 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 370 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 371 .flags = PCI_REGION_MEM, 372 }, 373 { 374 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 375 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 376 .size = CONFIG_SYS_PCIE1_IO_SIZE, 377 .flags = PCI_REGION_IO, 378 }, 379 }; 380 381 void pci_init_board(void) 382 { 383 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 384 sysconf83xx_t *sysconf = &immr->sysconf; 385 law83xx_t *pcie_law = sysconf->pcielaw; 386 struct pci_region *pcie_reg[] = { pcie_regions_0 }; 387 388 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 389 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 390 391 /* Deassert the resets in the control register */ 392 out_be32(&sysconf->pecr1, 0xE0008000); 393 udelay(2000); 394 395 /* Configure PCI Express Local Access Windows */ 396 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 397 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 398 399 mpc83xx_pcie_init(1, pcie_reg); 400 } 401 402 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 403 { 404 info->portwidth = FLASH_CFI_16BIT; 405 info->chipwidth = FLASH_CFI_BY16; 406 info->interface = FLASH_CFI_X16; 407 return 1; 408 } 409 410 #if defined(CONFIG_OF_BOARD_SETUP) 411 int ft_board_setup(void *blob, bd_t *bd) 412 { 413 ft_cpu_setup(blob, bd); 414 fsl_fdt_fixup_dr_usb(blob, bd); 415 fdt_fixup_esdhc(blob, bd); 416 417 return 0; 418 } 419 #endif 420 421 /* 422 * FPGA MII bitbang implementation 423 */ 424 425 struct fpga_mii { 426 unsigned fpga; 427 int mdio; 428 } fpga_mii[] = { 429 { 0, 1}, 430 { 1, 1}, 431 { 2, 1}, 432 { 3, 1}, 433 }; 434 435 static int mii_dummy_init(struct bb_miiphy_bus *bus) 436 { 437 return 0; 438 } 439 440 static int mii_mdio_active(struct bb_miiphy_bus *bus) 441 { 442 struct fpga_mii *fpga_mii = bus->priv; 443 444 if (fpga_mii->mdio) 445 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 446 else 447 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 448 449 return 0; 450 } 451 452 static int mii_mdio_tristate(struct bb_miiphy_bus *bus) 453 { 454 struct fpga_mii *fpga_mii = bus->priv; 455 456 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 457 458 return 0; 459 } 460 461 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) 462 { 463 struct fpga_mii *fpga_mii = bus->priv; 464 465 if (v) 466 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 467 else 468 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 469 470 fpga_mii->mdio = v; 471 472 return 0; 473 } 474 475 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) 476 { 477 u16 gpio; 478 struct fpga_mii *fpga_mii = bus->priv; 479 480 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); 481 482 *v = ((gpio & GPIO_MDIO) != 0); 483 484 return 0; 485 } 486 487 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) 488 { 489 struct fpga_mii *fpga_mii = bus->priv; 490 491 if (v) 492 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); 493 else 494 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); 495 496 return 0; 497 } 498 499 static int mii_delay(struct bb_miiphy_bus *bus) 500 { 501 udelay(1); 502 503 return 0; 504 } 505 506 struct bb_miiphy_bus bb_miiphy_buses[] = { 507 { 508 .name = "board0", 509 .init = mii_dummy_init, 510 .mdio_active = mii_mdio_active, 511 .mdio_tristate = mii_mdio_tristate, 512 .set_mdio = mii_set_mdio, 513 .get_mdio = mii_get_mdio, 514 .set_mdc = mii_set_mdc, 515 .delay = mii_delay, 516 .priv = &fpga_mii[0], 517 }, 518 { 519 .name = "board1", 520 .init = mii_dummy_init, 521 .mdio_active = mii_mdio_active, 522 .mdio_tristate = mii_mdio_tristate, 523 .set_mdio = mii_set_mdio, 524 .get_mdio = mii_get_mdio, 525 .set_mdc = mii_set_mdc, 526 .delay = mii_delay, 527 .priv = &fpga_mii[1], 528 }, 529 { 530 .name = "board2", 531 .init = mii_dummy_init, 532 .mdio_active = mii_mdio_active, 533 .mdio_tristate = mii_mdio_tristate, 534 .set_mdio = mii_set_mdio, 535 .get_mdio = mii_get_mdio, 536 .set_mdc = mii_set_mdc, 537 .delay = mii_delay, 538 .priv = &fpga_mii[2], 539 }, 540 { 541 .name = "board3", 542 .init = mii_dummy_init, 543 .mdio_active = mii_mdio_active, 544 .mdio_tristate = mii_mdio_tristate, 545 .set_mdio = mii_set_mdio, 546 .get_mdio = mii_get_mdio, 547 .set_mdc = mii_set_mdc, 548 .delay = mii_delay, 549 .priv = &fpga_mii[3], 550 }, 551 }; 552 553 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / 554 sizeof(bb_miiphy_buses[0]); 555