1 /* 2 * board/renesas/stout/stout.c 3 * This file is Stout board support. 4 * 5 * Copyright (C) 2015 Renesas Electronics Europe GmbH 6 * Copyright (C) 2015 Renesas Electronics Corporation 7 * Copyright (C) 2015 Cogent Embedded, Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #include <common.h> 13 #include <malloc.h> 14 #include <netdev.h> 15 #include <dm.h> 16 #include <dm/platform_data/serial_sh.h> 17 #include <environment.h> 18 #include <asm/processor.h> 19 #include <asm/mach-types.h> 20 #include <asm/io.h> 21 #include <linux/errno.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/gpio.h> 24 #include <asm/arch/rmobile.h> 25 #include <asm/arch/rcar-mstp.h> 26 #include <asm/arch/mmc.h> 27 #include <asm/arch/sh_sdhi.h> 28 #include <miiphy.h> 29 #include <i2c.h> 30 #include <mmc.h> 31 #include "qos.h" 32 #include "cpld.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define CLK2MHZ(clk) (clk / 1000 / 1000) 37 void s_init(void) 38 { 39 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 40 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 41 42 /* Watchdog init */ 43 writel(0xA5A5A500, &rwdt->rwtcsra); 44 writel(0xA5A5A500, &swdt->swtcsra); 45 46 /* CPU frequency setting. Set to 1.4GHz */ 47 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 48 u32 stat = 0; 49 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 50 << PLL0_STC_BIT; 51 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 52 53 do { 54 stat = readl(PLLECR) & PLL0ST; 55 } while (stat == 0x0); 56 } 57 58 /* QoS(Quality-of-Service) Init */ 59 qos_init(); 60 } 61 62 #define TMU0_MSTP125 (1 << 25) 63 #define SCIFA0_MSTP204 (1 << 4) 64 #define SDHI0_MSTP314 (1 << 14) 65 #define SDHI2_MSTP312 (1 << 12) 66 #define ETHER_MSTP813 (1 << 13) 67 68 #define MSTPSR3 0xE6150048 69 #define SMSTPCR3 0xE615013C 70 71 #define SD2CKCR 0xE6150078 72 #define SD2_97500KHZ 0x7 73 74 int board_early_init_f(void) 75 { 76 /* TMU0 */ 77 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 78 /* SCIFA0 */ 79 mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); 80 /* ETHER */ 81 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 82 /* SDHI0,2 */ 83 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); 84 85 /* 86 * SD0 clock is set to 97.5MHz by default. 87 * Set SD2 to the 97.5MHz as well. 88 */ 89 writel(SD2_97500KHZ, SD2CKCR); 90 91 return 0; 92 } 93 94 int board_init(void) 95 { 96 /* adress of boot parameters */ 97 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 98 99 /* Init PFC controller */ 100 r8a7790_pinmux_init(); 101 102 cpld_init(); 103 104 #ifdef CONFIG_SH_ETHER 105 /* ETHER Enable */ 106 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 107 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 108 gpio_request(GPIO_FN_ETH_RXD0, NULL); 109 gpio_request(GPIO_FN_ETH_RXD1, NULL); 110 gpio_request(GPIO_FN_ETH_LINK, NULL); 111 gpio_request(GPIO_FN_ETH_REF_CLK, NULL); 112 gpio_request(GPIO_FN_ETH_MDIO, NULL); 113 gpio_request(GPIO_FN_ETH_TXD1, NULL); 114 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 115 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 116 gpio_request(GPIO_FN_ETH_TXD0, NULL); 117 gpio_request(GPIO_FN_ETH_MDC, NULL); 118 gpio_request(GPIO_FN_IRQ1, NULL); 119 120 gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */ 121 gpio_direction_output(GPIO_GP_3_31, 0); 122 mdelay(20); 123 gpio_set_value(GPIO_GP_3_31, 1); 124 udelay(1); 125 #endif 126 127 return 0; 128 } 129 130 #define CXR24 0xEE7003C0 /* MAC address high register */ 131 #define CXR25 0xEE7003C8 /* MAC address low register */ 132 int board_eth_init(bd_t *bis) 133 { 134 int ret = -ENODEV; 135 136 #ifdef CONFIG_SH_ETHER 137 u32 val; 138 unsigned char enetaddr[6]; 139 140 ret = sh_eth_initialize(bis); 141 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 142 return ret; 143 144 /* Set Mac address */ 145 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 146 enetaddr[2] << 8 | enetaddr[3]; 147 writel(val, CXR24); 148 149 val = enetaddr[4] << 8 | enetaddr[5]; 150 writel(val, CXR25); 151 #endif 152 153 return ret; 154 } 155 156 /* Stout has KSZ8041NL/RNL */ 157 #define PHY_CONTROL1 0x1E 158 #define PHY_LED_MODE 0xC0000 159 #define PHY_LED_MODE_ACK 0x4000 160 int board_phy_config(struct phy_device *phydev) 161 { 162 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 163 ret &= ~PHY_LED_MODE; 164 ret |= PHY_LED_MODE_ACK; 165 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 166 167 return 0; 168 } 169 170 int board_mmc_init(bd_t *bis) 171 { 172 int ret = -ENODEV; 173 174 #ifdef CONFIG_SH_SDHI 175 gpio_request(GPIO_FN_SD0_DAT0, NULL); 176 gpio_request(GPIO_FN_SD0_DAT1, NULL); 177 gpio_request(GPIO_FN_SD0_DAT2, NULL); 178 gpio_request(GPIO_FN_SD0_DAT3, NULL); 179 gpio_request(GPIO_FN_SD0_CLK, NULL); 180 gpio_request(GPIO_FN_SD0_CMD, NULL); 181 gpio_request(GPIO_FN_SD0_CD, NULL); 182 gpio_request(GPIO_FN_SD2_DAT0, NULL); 183 gpio_request(GPIO_FN_SD2_DAT1, NULL); 184 gpio_request(GPIO_FN_SD2_DAT2, NULL); 185 gpio_request(GPIO_FN_SD2_DAT3, NULL); 186 gpio_request(GPIO_FN_SD2_CLK, NULL); 187 gpio_request(GPIO_FN_SD2_CMD, NULL); 188 gpio_request(GPIO_FN_SD2_CD, NULL); 189 190 /* SDHI0 - needs CPLD mux setup */ 191 gpio_request(GPIO_GP_3_30, NULL); 192 gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */ 193 gpio_request(GPIO_GP_5_24, NULL); 194 gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ 195 196 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 197 SH_SDHI_QUIRK_16BIT_BUF); 198 if (ret) 199 return ret; 200 201 /* SDHI2 - needs CPLD mux setup */ 202 gpio_request(GPIO_GP_3_29, NULL); 203 gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */ 204 gpio_request(GPIO_GP_5_25, NULL); 205 gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ 206 207 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 208 #endif 209 return ret; 210 } 211 212 213 int dram_init(void) 214 { 215 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 216 217 return 0; 218 } 219 220 const struct rmobile_sysinfo sysinfo = { 221 CONFIG_ARCH_RMOBILE_BOARD_STRING 222 }; 223 224 static const struct sh_serial_platdata serial_platdata = { 225 .base = SCIFA0_BASE, 226 .type = PORT_SCIFA, 227 .clk = CONFIG_MP_CLK_FREQ, 228 }; 229 230 U_BOOT_DEVICE(stout_serials) = { 231 .name = "serial_sh", 232 .platdata = &serial_platdata, 233 }; 234