1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <lcd.h> 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/mipi_dsim.h> 18 #include <asm/arch/watchdog.h> 19 #include <asm/arch/power.h> 20 #include <power/pmic.h> 21 #include <usb/dwc2_udc.h> 22 #include <power/max8997_pmic.h> 23 #include <power/max8997_muic.h> 24 #include <power/battery.h> 25 #include <power/max17042_fg.h> 26 #include <power/pmic.h> 27 #include <libtizen.h> 28 #include <usb.h> 29 #include <usb_mass_storage.h> 30 31 #include "setup.h" 32 33 unsigned int board_rev; 34 35 #ifdef CONFIG_REVISION_TAG 36 u32 get_board_rev(void) 37 { 38 return board_rev; 39 } 40 #endif 41 42 static void check_hw_revision(void); 43 struct dwc2_plat_otg_data s5pc210_otg_data; 44 45 int exynos_init(void) 46 { 47 check_hw_revision(); 48 printf("HW Revision:\t0x%x\n", board_rev); 49 50 return 0; 51 } 52 53 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 54 static void trats_low_power_mode(void) 55 { 56 struct exynos4_clock *clk = 57 (struct exynos4_clock *)samsung_get_base_clock(); 58 struct exynos4_power *pwr = 59 (struct exynos4_power *)samsung_get_base_power(); 60 61 /* Power down CORE1 */ 62 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 63 writel(0x0, &pwr->arm_core1_configuration); 64 65 /* Change the APLL frequency */ 66 /* ENABLE (1 enable) | LOCKED (1 locked) */ 67 /* [31] | [29] */ 68 /* FSEL | MDIV | PDIV | SDIV */ 69 /* [27] | [25:16] | [13:8] | [2:0] */ 70 writel(0xa0c80604, &clk->apll_con0); 71 72 /* Change CPU0 clock divider */ 73 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 74 /* [30:28] | [26:24] | [22:20] | [18:16] */ 75 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 76 /* [14:12] | [10:8] | [6:4] | [2:0] */ 77 writel(0x00000100, &clk->div_cpu0); 78 79 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 80 while (readl(&clk->div_stat_cpu0) & 0x1111111) 81 continue; 82 83 /* Change clock divider ratio for DMC */ 84 /* DMCP_RATIO | DMCD_RATIO */ 85 /* [22:20] | [18:16] */ 86 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 87 /* [14:12] | [10:8] | [6:4] | [2:0] */ 88 writel(0x13113117, &clk->div_dmc0); 89 90 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 91 while (readl(&clk->div_stat_dmc0) & 0x11111111) 92 continue; 93 94 /* Turn off unnecessary power domains */ 95 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 96 writel(0x0, &pwr->cam_configuration); /* CAM */ 97 writel(0x0, &pwr->tv_configuration); /* TV */ 98 writel(0x0, &pwr->mfc_configuration); /* MFC */ 99 writel(0x0, &pwr->g3d_configuration); /* G3D */ 100 writel(0x0, &pwr->gps_configuration); /* GPS */ 101 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 102 103 /* Turn off unnecessary clocks */ 104 writel(0x0, &clk->gate_ip_cam); /* CAM */ 105 writel(0x0, &clk->gate_ip_tv); /* TV */ 106 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 107 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 108 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 109 writel(0x0, &clk->gate_ip_gps); /* GPS */ 110 } 111 #endif 112 113 int exynos_power_init(void) 114 { 115 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 116 int chrg, ret; 117 struct power_battery *pb; 118 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 119 120 /* 121 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected 122 * to logical I2C adapter 0 123 * 124 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected 125 * to logical I2C adapter 1 126 */ 127 ret = power_fg_init(I2C_9); 128 ret |= power_muic_init(I2C_5); 129 ret |= power_bat_init(0); 130 if (ret) 131 return ret; 132 133 p_fg = pmic_get("MAX17042_FG"); 134 if (!p_fg) { 135 puts("MAX17042_FG: Not found\n"); 136 return -ENODEV; 137 } 138 139 p_chrg = pmic_get("MAX8997_PMIC"); 140 if (!p_chrg) { 141 puts("MAX8997_PMIC: Not found\n"); 142 return -ENODEV; 143 } 144 145 p_muic = pmic_get("MAX8997_MUIC"); 146 if (!p_muic) { 147 puts("MAX8997_MUIC: Not found\n"); 148 return -ENODEV; 149 } 150 151 p_bat = pmic_get("BAT_TRATS"); 152 if (!p_bat) { 153 puts("BAT_TRATS: Not found\n"); 154 return -ENODEV; 155 } 156 157 p_fg->parent = p_bat; 158 p_chrg->parent = p_bat; 159 p_muic->parent = p_bat; 160 161 p_bat->low_power_mode = trats_low_power_mode; 162 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 163 164 pb = p_bat->pbat; 165 chrg = p_muic->chrg->chrg_type(p_muic); 166 debug("CHARGER TYPE: %d\n", chrg); 167 168 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 169 puts("No battery detected\n"); 170 return 0; 171 } 172 173 p_fg->fg->fg_battery_check(p_fg, p_bat); 174 175 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 176 puts("CHARGE Battery !\n"); 177 #endif 178 179 return 0; 180 } 181 182 static unsigned int get_hw_revision(void) 183 { 184 int hwrev = 0; 185 char str[10]; 186 int i; 187 188 /* hw_rev[3:0] == GPE1[3:0] */ 189 for (i = 0; i < 4; i++) { 190 int pin = i + EXYNOS4_GPIO_E10; 191 192 sprintf(str, "hw_rev%d", i); 193 gpio_request(pin, str); 194 gpio_cfg_pin(pin, S5P_GPIO_INPUT); 195 gpio_set_pull(pin, S5P_GPIO_PULL_NONE); 196 } 197 198 udelay(1); 199 200 for (i = 0; i < 4; i++) 201 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i); 202 203 debug("hwrev 0x%x\n", hwrev); 204 205 return hwrev; 206 } 207 208 static void check_hw_revision(void) 209 { 210 int hwrev; 211 212 hwrev = get_hw_revision(); 213 214 board_rev |= hwrev; 215 } 216 217 218 #ifdef CONFIG_USB_GADGET 219 static int s5pc210_phy_control(int on) 220 { 221 struct udevice *dev; 222 int reg, ret; 223 224 ret = pmic_get("max8997-pmic", &dev); 225 if (ret) 226 return ret; 227 228 if (on) { 229 reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL); 230 reg |= ENSAFEOUT1; 231 ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg); 232 if (ret) { 233 puts("MAX8997 setting error!\n"); 234 return ret; 235 } 236 reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL); 237 reg |= EN_LDO; 238 ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg); 239 if (ret) { 240 puts("MAX8997 setting error!\n"); 241 return ret; 242 } 243 reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL); 244 reg |= EN_LDO; 245 ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg); 246 if (ret) { 247 puts("MAX8997 setting error!\n"); 248 return ret; 249 } 250 } else { 251 reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL); 252 reg &= DIS_LDO; 253 ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg); 254 if (ret) { 255 puts("MAX8997 setting error!\n"); 256 return ret; 257 } 258 reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL); 259 reg &= DIS_LDO; 260 ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg); 261 if (ret) { 262 puts("MAX8997 setting error!\n"); 263 return ret; 264 } 265 reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL); 266 reg &= ~ENSAFEOUT1; 267 ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg); 268 if (ret) { 269 puts("MAX8997 setting error!\n"); 270 return ret; 271 } 272 273 } 274 275 return 0; 276 } 277 278 struct dwc2_plat_otg_data s5pc210_otg_data = { 279 .phy_control = s5pc210_phy_control, 280 .regs_phy = EXYNOS4_USBPHY_BASE, 281 .regs_otg = EXYNOS4_USBOTG_BASE, 282 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 283 .usb_flags = PHY0_SLEEP, 284 }; 285 286 int board_usb_init(int index, enum usb_init_type init) 287 { 288 debug("USB_udc_probe\n"); 289 return dwc2_udc_probe(&s5pc210_otg_data); 290 } 291 292 int g_dnl_board_usb_cable_connected(void) 293 { 294 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 295 struct pmic *muic = pmic_get("MAX8997_MUIC"); 296 if (!muic) 297 return 0; 298 299 return !!muic->chrg->chrg_type(muic); 300 #else 301 return false; 302 #endif 303 304 } 305 #endif 306 307 static void pmic_reset(void) 308 { 309 gpio_direction_output(EXYNOS4_GPIO_X07, 1); 310 gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE); 311 } 312 313 static void board_clock_init(void) 314 { 315 struct exynos4_clock *clk = 316 (struct exynos4_clock *)samsung_get_base_clock(); 317 318 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 319 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 320 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 321 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 322 323 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 324 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 325 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 326 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 327 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 328 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 329 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 330 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 331 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 332 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 333 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 334 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 335 336 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 337 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 338 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 339 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 340 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 341 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 342 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 343 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 344 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 345 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 346 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 347 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 348 349 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 350 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 351 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 352 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 353 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 354 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 355 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 356 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 357 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 358 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 359 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 360 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 361 } 362 363 static void board_power_init(void) 364 { 365 struct exynos4_power *pwr = 366 (struct exynos4_power *)samsung_get_base_power(); 367 368 /* PS HOLD */ 369 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 370 371 /* Set power down */ 372 writel(0, (unsigned int)&pwr->cam_configuration); 373 writel(0, (unsigned int)&pwr->tv_configuration); 374 writel(0, (unsigned int)&pwr->mfc_configuration); 375 writel(0, (unsigned int)&pwr->g3d_configuration); 376 writel(0, (unsigned int)&pwr->lcd1_configuration); 377 writel(0, (unsigned int)&pwr->gps_configuration); 378 writel(0, (unsigned int)&pwr->gps_alive_configuration); 379 380 /* It is necessary to power down core 1 */ 381 /* to successfully boot CPU1 in kernel */ 382 writel(0, (unsigned int)&pwr->arm_core1_configuration); 383 } 384 385 static void exynos_uart_init(void) 386 { 387 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 388 gpio_request(EXYNOS4_GPIO_Y47, "uart_sel"); 389 gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP); 390 gpio_direction_output(EXYNOS4_GPIO_Y47, 1); 391 } 392 393 int exynos_early_init_f(void) 394 { 395 wdt_stop(); 396 pmic_reset(); 397 board_clock_init(); 398 exynos_uart_init(); 399 board_power_init(); 400 401 return 0; 402 } 403 404 void exynos_reset_lcd(void) 405 { 406 gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); 407 gpio_direction_output(EXYNOS4_GPIO_Y45, 1); 408 udelay(10000); 409 gpio_direction_output(EXYNOS4_GPIO_Y45, 0); 410 udelay(10000); 411 gpio_direction_output(EXYNOS4_GPIO_Y45, 1); 412 } 413 414 int lcd_power(void) 415 { 416 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 417 int ret = 0; 418 struct pmic *p = pmic_get("MAX8997_PMIC"); 419 if (!p) 420 return -ENODEV; 421 422 if (pmic_probe(p)) 423 return 0; 424 425 /* LDO15 voltage: 2.2v */ 426 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 427 /* LDO13 voltage: 3.0v */ 428 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 429 430 if (ret) { 431 puts("MAX8997 LDO setting error!\n"); 432 return -1; 433 } 434 #endif 435 return 0; 436 } 437 438 int mipi_power(void) 439 { 440 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 441 int ret = 0; 442 struct pmic *p = pmic_get("MAX8997_PMIC"); 443 if (!p) 444 return -ENODEV; 445 446 if (pmic_probe(p)) 447 return 0; 448 449 /* LDO3 voltage: 1.1v */ 450 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 451 /* LDO4 voltage: 1.8v */ 452 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 453 454 if (ret) { 455 puts("MAX8997 LDO setting error!\n"); 456 return -1; 457 } 458 #endif 459 return 0; 460 } 461 462 #ifdef CONFIG_LCD 463 void exynos_lcd_misc_init(vidinfo_t *vid) 464 { 465 #ifdef CONFIG_TIZEN 466 get_tizen_logo_info(vid); 467 #endif 468 #ifdef CONFIG_S6E8AX0 469 s6e8ax0_init(); 470 env_set("lcdinfo", "lcd=s6e8ax0"); 471 #endif 472 } 473 #endif 474