1 /* 2 * Copyright (c) 2016 Rockchip, Inc. 3 * Authors: Daniel Meng <daniel.meng@rock-chips.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <dm.h> 9 #include <malloc.h> 10 #include <usb.h> 11 #include <watchdog.h> 12 #include <linux/errno.h> 13 #include <linux/compat.h> 14 #include <linux/usb/dwc3.h> 15 #include <power/regulator.h> 16 17 #include "xhci.h" 18 19 struct rockchip_xhci_platdata { 20 fdt_addr_t hcd_base; 21 fdt_addr_t phy_base; 22 struct udevice *vbus_supply; 23 }; 24 25 /* 26 * Contains pointers to register base addresses 27 * for the usb controller. 28 */ 29 struct rockchip_xhci { 30 struct usb_platdata usb_plat; 31 struct xhci_ctrl ctrl; 32 struct xhci_hccr *hcd; 33 struct dwc3 *dwc3_reg; 34 }; 35 36 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 37 { 38 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 39 struct udevice *child; 40 int ret = 0; 41 42 /* 43 * Get the base address for XHCI controller from the device node 44 */ 45 plat->hcd_base = dev_read_addr(dev); 46 if (plat->hcd_base == FDT_ADDR_T_NONE) { 47 pr_err("Can't get the XHCI register base address\n"); 48 return -ENXIO; 49 } 50 51 /* Get the base address for usbphy from the device node */ 52 for (device_find_first_child(dev, &child); child; 53 device_find_next_child(&child)) { 54 if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy")) 55 continue; 56 plat->phy_base = devfdt_get_addr(child); 57 break; 58 } 59 60 if (plat->phy_base == FDT_ADDR_T_NONE) { 61 pr_err("Can't get the usbphy register address\n"); 62 return -ENXIO; 63 } 64 65 /* Vbus regulator */ 66 ret = device_get_supply_regulator(dev, "vbus-supply", 67 &plat->vbus_supply); 68 if (ret) 69 debug("Can't get VBus regulator!\n"); 70 71 return 0; 72 } 73 74 /* 75 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core 76 * @dwc: Pointer to our controller context structure 77 * @dev: Pointer to ulcass device 78 */ 79 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, 80 struct udevice *dev) 81 { 82 u32 reg; 83 u32 utmi_bits; 84 85 /* Set dwc3 usb2 phy config */ 86 reg = readl(&dwc3_reg->g_usb2phycfg[0]); 87 88 if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) 89 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 90 91 utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1); 92 if (utmi_bits == 16) { 93 reg |= DWC3_GUSB2PHYCFG_PHYIF; 94 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 95 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 96 } else if (utmi_bits == 8) { 97 reg &= ~DWC3_GUSB2PHYCFG_PHYIF; 98 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 99 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; 100 } 101 102 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) 103 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 104 105 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) 106 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 107 108 writel(reg, &dwc3_reg->g_usb2phycfg[0]); 109 } 110 111 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, 112 struct udevice *dev) 113 { 114 int ret; 115 116 ret = dwc3_core_init(rkxhci->dwc3_reg); 117 if (ret) { 118 pr_err("failed to initialize core\n"); 119 return ret; 120 } 121 122 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); 123 124 /* We are hard-coding DWC3 core to Host Mode */ 125 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 126 127 return 0; 128 } 129 130 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) 131 { 132 return 0; 133 } 134 135 static int xhci_usb_probe(struct udevice *dev) 136 { 137 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 138 struct rockchip_xhci *ctx = dev_get_priv(dev); 139 struct xhci_hcor *hcor; 140 int ret; 141 142 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 143 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 144 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + 145 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 146 147 if (plat->vbus_supply) { 148 ret = regulator_set_enable(plat->vbus_supply, true); 149 if (ret) { 150 pr_err("XHCI: failed to set VBus supply\n"); 151 return ret; 152 } 153 } 154 155 ret = rockchip_xhci_core_init(ctx, dev); 156 if (ret) { 157 pr_err("XHCI: failed to initialize controller\n"); 158 return ret; 159 } 160 161 return xhci_register(dev, ctx->hcd, hcor); 162 } 163 164 static int xhci_usb_remove(struct udevice *dev) 165 { 166 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 167 struct rockchip_xhci *ctx = dev_get_priv(dev); 168 int ret; 169 170 ret = xhci_deregister(dev); 171 if (ret) 172 return ret; 173 ret = rockchip_xhci_core_exit(ctx); 174 if (ret) 175 return ret; 176 177 if (plat->vbus_supply) { 178 ret = regulator_set_enable(plat->vbus_supply, false); 179 if (ret) 180 pr_err("XHCI: failed to set VBus supply\n"); 181 } 182 183 return ret; 184 } 185 186 static const struct udevice_id xhci_usb_ids[] = { 187 { .compatible = "rockchip,rk3399-xhci" }, 188 { .compatible = "rockchip,rk3328-xhci" }, 189 { } 190 }; 191 192 U_BOOT_DRIVER(usb_xhci) = { 193 .name = "xhci_rockchip", 194 .id = UCLASS_USB, 195 .of_match = xhci_usb_ids, 196 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 197 .probe = xhci_usb_probe, 198 .remove = xhci_usb_remove, 199 .ops = &xhci_usb_ops, 200 .bind = dm_scan_fdt_dev, 201 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), 202 .priv_auto_alloc_size = sizeof(struct rockchip_xhci), 203 .flags = DM_FLAG_ALLOC_PRIV_DMA, 204 }; 205 206 static const struct udevice_id usb_phy_ids[] = { 207 { .compatible = "rockchip,rk3399-usb3-phy" }, 208 { .compatible = "rockchip,rk3328-usb3-phy" }, 209 { } 210 }; 211 212 U_BOOT_DRIVER(usb_phy) = { 213 .name = "usb_phy_rockchip", 214 .of_match = usb_phy_ids, 215 }; 216