1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 DENX Software Engineering 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mx6-ddr.h> 15 #include <asm/arch/sys_proto.h> 16 #include <errno.h> 17 #include <asm/gpio.h> 18 #include <malloc.h> 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <asm/mach-imx/mxc_i2c.h> 21 #include <asm/mach-imx/boot_mode.h> 22 #include <asm/mach-imx/spi.h> 23 #include <mmc.h> 24 #include <fsl_esdhc.h> 25 #include <miiphy.h> 26 #include <netdev.h> 27 #include <i2c.h> 28 29 #include <dm.h> 30 #include <dm/platform_data/serial_mxc.h> 31 #include <dm/platdata.h> 32 33 #ifndef CONFIG_MXC_SPI 34 #error "CONFIG_SPI must be set for this board" 35 #error "Please check your config file" 36 #endif 37 38 #include "common.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 static bool hw_ids_valid; 43 static bool sw_ids_valid; 44 static u32 cpu_id; 45 static u32 unit_id; 46 47 #define SW0 IMX_GPIO_NR(2, 4) 48 #define SW1 IMX_GPIO_NR(2, 5) 49 #define SW2 IMX_GPIO_NR(2, 6) 50 #define SW3 IMX_GPIO_NR(2, 7) 51 #define HW0 IMX_GPIO_NR(6, 7) 52 #define HW1 IMX_GPIO_NR(6, 9) 53 #define HW2 IMX_GPIO_NR(6, 10) 54 #define HW3 IMX_GPIO_NR(6, 11) 55 #define HW4 IMX_GPIO_NR(4, 7) 56 #define HW5 IMX_GPIO_NR(4, 11) 57 #define HW6 IMX_GPIO_NR(4, 13) 58 #define HW7 IMX_GPIO_NR(4, 15) 59 60 int gpio_table_sw_ids[] = { 61 SW0, SW1, SW2, SW3 62 }; 63 64 const char *gpio_table_sw_ids_names[] = { 65 "sw0", "sw1", "sw2", "sw3" 66 }; 67 68 int gpio_table_hw_ids[] = { 69 HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 70 }; 71 72 const char *gpio_table_hw_ids_names[] = { 73 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" 74 }; 75 76 static int get_board_id(int *ids, const char **c, int size, 77 bool *valid, u32 *id) 78 { 79 int i, ret, val; 80 81 *valid = false; 82 83 for (i = 0; i < size; i++) { 84 ret = gpio_request(ids[i], c[i]); 85 if (ret) { 86 printf("Can't request SWx gpios\n"); 87 return ret; 88 } 89 } 90 91 for (i = 0; i < size; i++) { 92 ret = gpio_direction_input(ids[i]); 93 if (ret) { 94 printf("Can't set SWx gpios direction\n"); 95 return ret; 96 } 97 } 98 99 for (i = 0; i < size; i++) { 100 val = gpio_get_value(ids[i]); 101 if (val < 0) { 102 printf("Can't get SW%d ID\n", i); 103 *id = 0; 104 return val; 105 } 106 *id |= val << i; 107 } 108 *valid = true; 109 110 return 0; 111 } 112 113 int dram_init(void) 114 { 115 gd->ram_size = imx_ddr_size(); 116 117 return 0; 118 } 119 120 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 121 /* I2C1: TFA9879 */ 122 struct i2c_pads_info i2c_pad_info0 = { 123 .scl = { 124 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 125 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 126 .gp = IMX_GPIO_NR(3, 21) 127 }, 128 .sda = { 129 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 130 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 131 .gp = IMX_GPIO_NR(3, 28) 132 } 133 }; 134 135 /* I2C2: TIVO TM4C123 */ 136 struct i2c_pads_info i2c_pad_info1 = { 137 .scl = { 138 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 139 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 140 .gp = IMX_GPIO_NR(2, 30) 141 }, 142 .sda = { 143 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 144 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 145 .gp = IMX_GPIO_NR(3, 16) 146 } 147 }; 148 149 /* I2C3: PMIC PF0100, EEPROM AT24C256C */ 150 struct i2c_pads_info i2c_pad_info2 = { 151 .scl = { 152 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 153 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 154 .gp = IMX_GPIO_NR(3, 17) 155 }, 156 .sda = { 157 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 158 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 159 .gp = IMX_GPIO_NR(3, 18) 160 } 161 }; 162 163 iomux_v3_cfg_t const misc_pads[] = { 164 /* Prod ID GPIO pins */ 165 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 166 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 170 /* HW revision GPIO pins */ 171 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 175 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 177 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 179 180 /* XTALOSC */ 181 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL), 182 }; 183 184 #ifdef CONFIG_FSL_ESDHC 185 struct fsl_esdhc_cfg usdhc_cfg[1] = { 186 { USDHC4_BASE_ADDR, 0, 8, }, 187 }; 188 189 int board_mmc_getcd(struct mmc *mmc) 190 { 191 return 1; 192 } 193 194 int board_mmc_init(bd_t *bis) 195 { 196 displ5_set_iomux_usdhc(); 197 198 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 199 200 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 201 } 202 #endif /* CONFIG_FSL_ESDHC */ 203 204 static void displ5_setup_ecspi(void) 205 { 206 int ret; 207 208 displ5_set_iomux_ecspi(); 209 210 ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); 211 if (!ret) 212 gpio_direction_output(IMX_GPIO_NR(5, 29), 1); 213 214 ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); 215 if (!ret) 216 gpio_direction_output(IMX_GPIO_NR(7, 0), 1); 217 } 218 219 #ifdef CONFIG_FEC_MXC 220 iomux_v3_cfg_t const enet_pads[] = { 221 MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL), 222 MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), 223 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 224 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 225 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 226 227 /* for old evalboard with R159 present and R160 not populated */ 228 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 229 230 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 231 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 232 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 233 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 234 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 235 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 236 237 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 238 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 239 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 240 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 241 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 242 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 243 /*INT#_GBE*/ 244 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 245 }; 246 247 static void setup_iomux_enet(void) 248 { 249 SETUP_IOMUX_PADS(enet_pads); 250 gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ 251 } 252 253 int board_eth_init(bd_t *bd) 254 { 255 struct phy_device *phydev; 256 struct mii_dev *bus; 257 int ret; 258 259 setup_iomux_enet(); 260 261 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); 262 263 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 264 if (ret) 265 return ret; 266 267 bus = fec_get_miibus(IMX_FEC_BASE, -1); 268 if (!bus) 269 return -ENODEV; 270 271 /* 272 * We use here the "rgmii-id" mode of operation and allow M88E1512 273 * PHY to use its internally callibrated RX/TX delays 274 */ 275 phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, 276 PHY_INTERFACE_MODE_RGMII_ID); 277 if (!phydev) { 278 ret = -ENODEV; 279 goto err_phy; 280 } 281 282 /* display5 due to PCB routing can only work with 100 Mbps */ 283 phydev->advertising &= ~(ADVERTISED_1000baseX_Half | 284 ADVERTISED_1000baseX_Full | 285 SUPPORTED_1000baseT_Half | 286 SUPPORTED_1000baseT_Full); 287 288 ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); 289 if (ret) 290 goto err_sw; 291 292 return 0; 293 294 err_sw: 295 free(phydev); 296 err_phy: 297 mdio_unregister(bus); 298 free(bus); 299 return ret; 300 } 301 #endif /* CONFIG_FEC_MXC */ 302 303 /* 304 * Do not overwrite the console 305 * Always use serial for U-Boot console 306 */ 307 int overwrite_console(void) 308 { 309 return 1; 310 } 311 312 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 313 int ft_board_setup(void *blob, bd_t *bd) 314 { 315 fdt_fixup_ethernet(blob); 316 return 0; 317 } 318 #endif 319 320 int board_init(void) 321 { 322 debug("board init\n"); 323 /* address of boot parameters */ 324 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 325 326 /* Setup iomux for non console UARTS */ 327 displ5_set_iomux_uart(); 328 329 displ5_setup_ecspi(); 330 331 SETUP_IOMUX_PADS(misc_pads); 332 333 get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], 334 ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id); 335 debug("SWx unit_id 0x%x\n", unit_id); 336 337 get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0], 338 ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id); 339 debug("HWx cpu_id 0x%x\n", cpu_id); 340 341 if (hw_ids_valid && sw_ids_valid) 342 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id); 343 344 udelay(25); 345 346 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 347 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 348 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 349 350 return 0; 351 } 352 353 #ifdef CONFIG_CMD_BMODE 354 static const struct boot_mode board_boot_modes[] = { 355 /* eMMC, USDHC-4, 8-bit bus width */ 356 /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */ 357 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, 358 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)}, 359 {NULL, 0}, 360 }; 361 362 static void setup_boot_modes(void) 363 { 364 add_board_boot_modes(board_boot_modes); 365 } 366 #else 367 static inline void setup_boot_modes(void) {} 368 #endif 369 370 int misc_init_r(void) 371 { 372 setup_boot_modes(); 373 return 0; 374 } 375 376 static struct mxc_serial_platdata mxc_serial_plat = { 377 .reg = (struct mxc_uart *)UART5_BASE, 378 }; 379 380 U_BOOT_DEVICE(mxc_serial) = { 381 .name = "serial_mxc", 382 .platdata = &mxc_serial_plat, 383 }; 384