1 /* 2 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <linux/libfdt.h> 11 #include <asm/io.h> 12 #include <asm/system.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include <asm/armv8/mmu.h> 16 17 /* Armada 3700 */ 18 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800)) 19 20 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8) 21 #define MVEBU_XTAL_MODE_MASK BIT(9) 22 #define MVEBU_XTAL_MODE_OFFS 9 23 #define MVEBU_XTAL_CLOCK_25MHZ 0x0 24 #define MVEBU_XTAL_CLOCK_40MHZ 0x1 25 26 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40) 27 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e 28 29 static struct mm_region mvebu_mem_map[] = { 30 { 31 /* RAM */ 32 .phys = 0x0UL, 33 .virt = 0x0UL, 34 .size = 0x80000000UL, 35 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 36 PTE_BLOCK_INNER_SHARE 37 }, 38 { 39 /* SRAM, MMIO regions */ 40 .phys = 0xd0000000UL, 41 .virt = 0xd0000000UL, 42 .size = 0x02000000UL, /* 32MiB internal registers */ 43 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 44 PTE_BLOCK_NON_SHARE 45 }, 46 { 47 /* PCI regions */ 48 .phys = 0xe8000000UL, 49 .virt = 0xe8000000UL, 50 .size = 0x02000000UL, /* 32MiB master PCI space */ 51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 52 PTE_BLOCK_NON_SHARE 53 }, 54 { 55 /* List terminator */ 56 0, 57 } 58 }; 59 60 struct mm_region *mem_map = mvebu_mem_map; 61 62 void reset_cpu(ulong ignored) 63 { 64 /* 65 * Write magic number of 0x1d1e to North Bridge Warm Reset register 66 * to trigger warm reset 67 */ 68 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG); 69 } 70 71 /* 72 * get_ref_clk 73 * 74 * return: reference clock in MHz (25 or 40) 75 */ 76 u32 get_ref_clk(void) 77 { 78 u32 regval; 79 80 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> 81 MVEBU_XTAL_MODE_OFFS; 82 83 if (regval == MVEBU_XTAL_CLOCK_25MHZ) 84 return 25; 85 else 86 return 40; 87 } 88