1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2008-2012 Freescale Semiconductor, Inc. 4 * Kumar Gala <kumar.gala@freescale.com> 5 */ 6 7#include <asm-offsets.h> 8#include <config.h> 9#include <mpc85xx.h> 10 11#include <ppc_asm.tmpl> 12#include <ppc_defs.h> 13 14#include <asm/cache.h> 15#include <asm/mmu.h> 16 17/* To boot secondary cpus, we need a place for them to start up. 18 * Normally, they start at 0xfffffffc, but that's usually the 19 * firmware, and we don't want to have to run the firmware again. 20 * Instead, the primary cpu will set the BPTR to point here to 21 * this page. We then set up the core, and head to 22 * start_secondary. Note that this means that the code below 23 * must never exceed 1023 instructions (the branch at the end 24 * would then be the 1024th). 25 */ 26 .globl __secondary_start_page 27 .align 12 28__secondary_start_page: 29/* First do some preliminary setup */ 30 lis r3, HID0_EMCP@h /* enable machine check */ 31#ifndef CONFIG_E500MC 32 ori r3,r3,HID0_TBEN@l /* enable Timebase */ 33#endif 34#ifdef CONFIG_PHYS_64BIT 35 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ 36#endif 37 mtspr SPRN_HID0,r3 38 39#ifndef CONFIG_E500MC 40 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 41 mfspr r0,PVR 42 andi. r0,r0,0xff 43 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ 44 blt 1f 45 /* Set MBDD bit also */ 46 ori r3, r3, HID1_MBDD@l 471: 48 mtspr SPRN_HID1,r3 49#endif 50 51#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 52 mfspr r3,SPRN_HDBCR1 53 oris r3,r3,0x0100 54 mtspr SPRN_HDBCR1,r3 55#endif 56 57#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 58 mfspr r3,SPRN_SVR 59 rlwinm r3,r3,0,0xff 60 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 61 cmpw r3,r4 62 beq 1f 63 64#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 65 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 66 cmpw r3,r4 67 beq 1f 68#endif 69 70 /* Not a supported revision affected by erratum */ 71 b 2f 72 731: /* Erratum says set bits 55:60 to 001001 */ 74 msync 75 isync 76 mfspr r3,SPRN_HDBCR0 77 li r4,0x48 78 rlwimi r3,r4,0,0x1f8 79 mtspr SPRN_HDBCR0,r3 80 isync 812: 82#endif 83 84 /* Enable branch prediction */ 85 lis r3,BUCSR_ENABLE@h 86 ori r3,r3,BUCSR_ENABLE@l 87 mtspr SPRN_BUCSR,r3 88 89 /* Ensure TB is 0 */ 90 li r3,0 91 mttbl r3 92 mttbu r3 93 94 /* Enable/invalidate the I-Cache */ 95 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 96 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 97 mtspr SPRN_L1CSR1,r2 981: 99 mfspr r3,SPRN_L1CSR1 100 and. r1,r3,r2 101 bne 1b 102 103 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 104 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 105 mtspr SPRN_L1CSR1,r3 106 isync 1072: 108 mfspr r3,SPRN_L1CSR1 109 andi. r1,r3,L1CSR1_ICE@l 110 beq 2b 111 112 /* Enable/invalidate the D-Cache */ 113 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 114 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 115 mtspr SPRN_L1CSR0,r2 1161: 117 mfspr r3,SPRN_L1CSR0 118 and. r1,r3,r2 119 bne 1b 120 121 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 122 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 123 mtspr SPRN_L1CSR0,r3 124 isync 1252: 126 mfspr r3,SPRN_L1CSR0 127 andi. r1,r3,L1CSR0_DCE@l 128 beq 2b 129 130#define toreset(x) (x - __secondary_start_page + 0xfffff000) 131 132 /* get our PIR to figure out our table entry */ 133 lis r3,toreset(__spin_table_addr)@h 134 ori r3,r3,toreset(__spin_table_addr)@l 135 lwz r3,0(r3) 136 137 mfspr r0,SPRN_PIR 138#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 139/* 140 * PIR definition for Chassis 2 141 * 0-17 Reserved (logic 0s) 142 * 18-19 CHIP_ID, 2'b00 - SoC 1 143 * all others - reserved 144 * 20-24 CLUSTER_ID 5'b00000 - CCM 1 145 * all others - reserved 146 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 147 * 2'b01 - cluster 2 148 * 2'b10 - cluster 3 149 * 2'b11 - cluster 4 150 * 27-28 CORE_ID 2'b00 - core 0 151 * 2'b01 - core 1 152 * 2'b10 - core 2 153 * 2'b11 - core 3 154 * 29-31 THREAD_ID 3'b000 - thread 0 155 * 3'b001 - thread 1 156 * 157 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08 158 * and clusters by 0x20. 159 * 160 * We renumber PIR so that all threads in the system are consecutive. 161 */ 162 163 rlwinm r8,r0,29,0x03 /* r8 = core within cluster */ 164 srwi r10,r0,5 /* r10 = cluster */ 165 166 mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER 167 add r5,r5,r8 /* for spin table index */ 168 mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */ 169#elif defined(CONFIG_E500MC) 170 rlwinm r4,r0,27,27,31 171 mr r5,r4 172#else 173 mr r4,r0 174 mr r5,r4 175#endif 176 177 /* 178 * r10 has the base address for the entry. 179 * we cannot access it yet before setting up a new TLB 180 */ 181 slwi r8,r5,6 /* spin table is padded to 64 byte */ 182 add r10,r3,r8 183 184 mtspr SPRN_PIR,r4 /* write to PIR register */ 185 186#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 187 mfspr r8, L1CSR2 188 clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */ 189 mtspr L1CSR2, r8 190#else 191#ifdef CONFIG_SYS_CACHE_STASHING 192 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 193 slwi r8,r4,1 194 addi r8,r8,32 195 mtspr L1CSR2,r8 196#endif 197#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */ 198 199#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 200 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 201 /* 202 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 203 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 204 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 205 */ 206 mfspr r3,SPRN_SVR 207 rlwinm r6,r3,24,~0x800 /* clear E bit */ 208 209 lis r5,SVR_P4080@h 210 ori r5,r5,SVR_P4080@l 211 cmpw r6,r5 212 bne 1f 213 214 rlwinm r3,r3,0,0xf0 215 li r5,0x30 216 cmpw r3,r5 217 bge 2f 2181: 219#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 220 lis r3,toreset(enable_cpu_a011_workaround)@ha 221 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) 222 cmpwi r3,0 223 beq 2f 224#endif 225 mfspr r3,L1CSR2 226 oris r3,r3,(L1CSR2_DCWS)@h 227 mtspr L1CSR2,r3 2282: 229#endif 230 231#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 232 /* 233 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in 234 * write shadow mode. This code should run after other code setting 235 * DCWS. 236 */ 237 mfspr r3,L1CSR2 238 andis. r3,r3,(L1CSR2_DCWS)@h 239 beq 1f 240 mfspr r3, SPRN_HDBCR0 241 oris r3, r3, 0x8000 242 mtspr SPRN_HDBCR0, r3 2431: 244#endif 245 246#ifdef CONFIG_BACKSIDE_L2_CACHE 247 /* skip L2 setup on P2040/P2040E as they have no L2 */ 248 mfspr r3,SPRN_SVR 249 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ 250 251 lis r3,SVR_P2040@h 252 ori r3,r3,SVR_P2040@l 253 cmpw r6,r3 254 beq 3f 255 256 /* Enable/invalidate the L2 cache */ 257 msync 258 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h 259 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l 260 mtspr SPRN_L2CSR0,r2 2611: 262 mfspr r3,SPRN_L2CSR0 263 and. r1,r3,r2 264 bne 1b 265 266#ifdef CONFIG_SYS_CACHE_STASHING 267 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 268 addi r3,r8,1 269 mtspr SPRN_L2CSR1,r3 270#endif 271 272 lis r3,CONFIG_SYS_INIT_L2CSR0@h 273 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l 274 mtspr SPRN_L2CSR0,r3 275 isync 2762: 277 mfspr r3,SPRN_L2CSR0 278 andis. r1,r3,L2CSR0_L2E@h 279 beq 2b 280#endif 2813: 282 /* setup mapping for the spin table, WIMGE=0b00100 */ 283 lis r13,toreset(__spin_table_addr)@h 284 ori r13,r13,toreset(__spin_table_addr)@l 285 lwz r13,0(r13) 286 /* mask by 4K */ 287 rlwinm r13,r13,0,0,19 288 289 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h 290 mtspr SPRN_MAS0,r11 291 lis r11,(MAS1_VALID|MAS1_IPROT)@h 292 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 293 mtspr SPRN_MAS1,r11 294 oris r11,r13,(MAS2_M|MAS2_G)@h 295 ori r11,r13,(MAS2_M|MAS2_G)@l 296 mtspr SPRN_MAS2,r11 297 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h 298 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l 299 mtspr SPRN_MAS3,r11 300 li r11,0 301 mtspr SPRN_MAS7,r11 302 tlbwe 303 304 /* 305 * __bootpg_addr has the address of __second_half_boot_page 306 * jump there in AS=1 space with cache enabled 307 */ 308 lis r13,toreset(__bootpg_addr)@h 309 ori r13,r13,toreset(__bootpg_addr)@l 310 lwz r11,0(r13) 311 mtspr SPRN_SRR0,r11 312 mfmsr r13 313 ori r12,r13,MSR_IS|MSR_DS@l 314 mtspr SPRN_SRR1,r12 315 rfi 316 317 /* 318 * Allocate some space for the SDRAM address of the bootpg. 319 * This variable has to be in the boot page so that it can 320 * be accessed by secondary cores when they come out of reset. 321 */ 322 .align L1_CACHE_SHIFT 323 .globl __bootpg_addr 324__bootpg_addr: 325 .long 0 326 327 .global __spin_table_addr 328__spin_table_addr: 329 .long 0 330 331 /* 332 * This variable is set by cpu_init_r() after parsing hwconfig 333 * to enable workaround for erratum NMG_CPU_A011. 334 */ 335 .align L1_CACHE_SHIFT 336 .global enable_cpu_a011_workaround 337enable_cpu_a011_workaround: 338 .long 1 339 340 /* Fill in the empty space. The actual reset vector is 341 * the last word of the page */ 342__secondary_start_code_end: 343 .space 4092 - (__secondary_start_code_end - __secondary_start_page) 344__secondary_reset_vector: 345 b __secondary_start_page 346 347 348/* this is a separated page for the spin table and cacheable boot code */ 349 .align L1_CACHE_SHIFT 350 .global __second_half_boot_page 351__second_half_boot_page: 352#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE 353 lis r3,(spin_table_compat - __second_half_boot_page)@h 354 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l 355 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */ 356 lwz r14,0(r3) 357#endif 358 359#define ENTRY_ADDR_UPPER 0 360#define ENTRY_ADDR_LOWER 4 361#define ENTRY_R3_UPPER 8 362#define ENTRY_R3_LOWER 12 363#define ENTRY_RESV 16 364#define ENTRY_PIR 20 365#define ENTRY_SIZE 64 366 /* 367 * setup the entry 368 * r10 has the base address of the spin table. 369 * spin table is defined as 370 * struct { 371 * uint64_t entry_addr; 372 * uint64_t r3; 373 * uint32_t rsvd1; 374 * uint32_t pir; 375 * }; 376 * we pad this struct to 64 bytes so each entry is in its own cacheline 377 */ 378 li r3,0 379 li r8,1 380 mfspr r4,SPRN_PIR 381 stw r3,ENTRY_ADDR_UPPER(r10) 382 stw r3,ENTRY_R3_UPPER(r10) 383 stw r4,ENTRY_R3_LOWER(r10) 384 stw r3,ENTRY_RESV(r10) 385 stw r4,ENTRY_PIR(r10) 386 msync 387 stw r8,ENTRY_ADDR_LOWER(r10) 388 389 /* spin waiting for addr */ 3903: 391/* 392 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled 393 * memory. Old OS may not work with this change. A patch is waiting to be 394 * accepted for Linux kernel. Other OS needs similar fix to spin table. 395 * For OSes with old spin table code, we can enable this temporary fix by 396 * setting environmental variable "spin_table_compat". For new OSes, set 397 * "spin_table_compat=no". After Linux is fixed, we can remove this macro 398 * and related code. For now, it is enabled by default. 399 */ 400#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE 401 cmpwi r14,0 402 beq 4f 403 dcbf 0, r10 404 sync 4054: 406#endif 407 lwz r4,ENTRY_ADDR_LOWER(r10) 408 andi. r11,r4,1 409 bne 3b 410 isync 411 412 /* get the upper bits of the addr */ 413 lwz r11,ENTRY_ADDR_UPPER(r10) 414 415 /* setup branch addr */ 416 mtspr SPRN_SRR0,r4 417 418 /* mark the entry as released */ 419 li r8,3 420 stw r8,ENTRY_ADDR_LOWER(r10) 421 422 /* mask by ~64M to setup our tlb we will jump to */ 423 rlwinm r12,r4,0,0,5 424 425 /* 426 * setup r3, r4, r5, r6, r7, r8, r9 427 * r3 contains the value to put in the r3 register at secondary cpu 428 * entry. The high 32-bits are ignored on 32-bit chip implementations. 429 * 64-bit chip implementations however shall load all 64-bits 430 */ 431#ifdef CONFIG_SYS_PPC64 432 ld r3,ENTRY_R3_UPPER(r10) 433#else 434 lwz r3,ENTRY_R3_LOWER(r10) 435#endif 436 li r4,0 437 li r5,0 438 li r6,0 439 lis r7,(64*1024*1024)@h 440 li r8,0 441 li r9,0 442 443 /* load up the pir */ 444 lwz r0,ENTRY_PIR(r10) 445 mtspr SPRN_PIR,r0 446 mfspr r0,SPRN_PIR 447 stw r0,ENTRY_PIR(r10) 448 449 mtspr IVPR,r12 450/* 451 * Coming here, we know the cpu has one TLB mapping in TLB1[0] 452 * which maps 0xfffff000-0xffffffff one-to-one. We set up a 453 * second mapping that maps addr 1:1 for 64M, and then we jump to 454 * addr 455 */ 456 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h 457 mtspr SPRN_MAS0,r10 458 lis r10,(MAS1_VALID|MAS1_IPROT)@h 459 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l 460 mtspr SPRN_MAS1,r10 461 /* WIMGE = 0b00000 for now */ 462 mtspr SPRN_MAS2,r12 463 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) 464 mtspr SPRN_MAS3,r12 465#ifdef CONFIG_ENABLE_36BIT_PHYS 466 mtspr SPRN_MAS7,r11 467#endif 468 tlbwe 469 470/* Now we have another mapping for this page, so we jump to that 471 * mapping 472 */ 473 mtspr SPRN_SRR1,r13 474 rfi 475 476 477 .align 6 478 .globl __spin_table 479__spin_table: 480 .space CONFIG_MAX_CPUS*ENTRY_SIZE 481 482#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE 483 .align L1_CACHE_SHIFT 484 .global spin_table_compat 485spin_table_compat: 486 .long 1 487 488#endif 489 490__spin_table_end: 491 .space 4096 - (__spin_table_end - __spin_table) 492