1 /* 2 * (C) Copyright 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 * 7 * Adapted from coreboot. 8 */ 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <dt-structs.h> 14 #include <errno.h> 15 #include <ram.h> 16 #include <regmap.h> 17 #include <syscon.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/cru_rk3288.h> 21 #include <asm/arch/ddr_rk3288.h> 22 #include <asm/arch/grf_rk3288.h> 23 #include <asm/arch/pmu_rk3288.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/sdram_common.h> 26 #include <linux/err.h> 27 #include <power/regulator.h> 28 #include <power/rk8xx_pmic.h> 29 30 struct chan_info { 31 struct rk3288_ddr_pctl *pctl; 32 struct rk3288_ddr_publ *publ; 33 struct rk3288_msch *msch; 34 }; 35 36 struct dram_info { 37 struct chan_info chan[2]; 38 struct ram_info info; 39 struct clk ddr_clk; 40 struct rk3288_cru *cru; 41 struct rk3288_grf *grf; 42 struct rk3288_sgrf *sgrf; 43 struct rk3288_pmu *pmu; 44 bool is_veyron; 45 }; 46 47 struct rk3288_sdram_params { 48 #if CONFIG_IS_ENABLED(OF_PLATDATA) 49 struct dtd_rockchip_rk3288_dmc of_plat; 50 #endif 51 struct rk3288_sdram_channel ch[2]; 52 struct rk3288_sdram_pctl_timing pctl_timing; 53 struct rk3288_sdram_phy_timing phy_timing; 54 struct rk3288_base_params base; 55 int num_channels; 56 struct regmap *map; 57 }; 58 59 const int ddrconf_table[] = { 60 /* row col,bw */ 61 0, 62 ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 63 ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 64 ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 65 ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), 66 ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), 67 ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), 68 ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), 69 ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), 70 ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), 71 ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), 72 0, 73 0, 74 0, 75 0, 76 ((4 << 4) | 2), 77 }; 78 79 #define TEST_PATTEN 0x5aa5f00f 80 #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) 81 #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) 82 83 #ifdef CONFIG_SPL_BUILD 84 static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 85 { 86 int i; 87 88 for (i = 0; i < n / sizeof(u32); i++) { 89 writel(*src, dest); 90 src++; 91 dest++; 92 } 93 } 94 95 static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) 96 { 97 u32 phy_ctl_srstn_shift = 4 + 5 * ch; 98 u32 ctl_psrstn_shift = 3 + 5 * ch; 99 u32 ctl_srstn_shift = 2 + 5 * ch; 100 u32 phy_psrstn_shift = 1 + 5 * ch; 101 u32 phy_srstn_shift = 5 * ch; 102 103 rk_clrsetreg(&cru->cru_softrst_con[10], 104 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | 105 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | 106 1 << phy_srstn_shift, 107 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | 108 ctl << ctl_srstn_shift | phy << phy_psrstn_shift | 109 phy << phy_srstn_shift); 110 } 111 112 static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) 113 { 114 u32 phy_ctl_srstn_shift = 4 + 5 * ch; 115 116 rk_clrsetreg(&cru->cru_softrst_con[10], 117 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); 118 } 119 120 static void phy_pctrl_reset(struct rk3288_cru *cru, 121 struct rk3288_ddr_publ *publ, 122 int channel) 123 { 124 int i; 125 126 ddr_reset(cru, channel, 1, 1); 127 udelay(1); 128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); 129 for (i = 0; i < 4; i++) 130 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); 131 132 udelay(10); 133 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); 134 for (i = 0; i < 4; i++) 135 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); 136 137 udelay(10); 138 ddr_reset(cru, channel, 1, 0); 139 udelay(10); 140 ddr_reset(cru, channel, 0, 0); 141 udelay(10); 142 } 143 144 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, 145 u32 freq) 146 { 147 int i; 148 149 if (freq <= 250000000) { 150 if (freq <= 150000000) 151 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); 152 else 153 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); 154 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); 155 for (i = 0; i < 4; i++) 156 setbits_le32(&publ->datx8[i].dxdllcr, 157 DXDLLCR_DLLDIS); 158 159 setbits_le32(&publ->pir, PIR_DLLBYP); 160 } else { 161 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); 162 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); 163 for (i = 0; i < 4; i++) { 164 clrbits_le32(&publ->datx8[i].dxdllcr, 165 DXDLLCR_DLLDIS); 166 } 167 168 clrbits_le32(&publ->pir, PIR_DLLBYP); 169 } 170 } 171 172 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) 173 { 174 writel(DFI_INIT_START, &pctl->dfistcfg0); 175 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, 176 &pctl->dfistcfg1); 177 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 178 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 179 &pctl->dfilpcfg0); 180 181 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); 182 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); 183 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); 184 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); 185 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); 186 writel(1, &pctl->dfitphyupdtype0); 187 188 /* cs0 and cs1 write odt enable */ 189 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), 190 &pctl->dfiodtcfg); 191 /* odt write length */ 192 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 193 /* phyupd and ctrlupd disabled */ 194 writel(0, &pctl->dfiupdcfg); 195 } 196 197 static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable) 198 { 199 uint val = 0; 200 201 if (enable) { 202 val = 1 << (channel ? DDR1_16BIT_EN_SHIFT : 203 DDR0_16BIT_EN_SHIFT); 204 } 205 rk_clrsetreg(&grf->soc_con0, 206 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT), 207 val); 208 } 209 210 static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel, 211 bool ddr3_mode) 212 { 213 uint mask, val; 214 215 mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT); 216 val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT : 217 MSCH0_MAINDDR3_SHIFT); 218 rk_clrsetreg(&grf->soc_con0, mask, val); 219 } 220 221 static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel, 222 bool enable, bool enable_bst, bool enable_odt) 223 { 224 uint mask; 225 bool disable_bst = !enable_bst; 226 227 mask = channel ? 228 (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT | 229 1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) : 230 (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT | 231 1 << UPCTL0_LPDDR3_ODT_EN_SHIFT); 232 rk_clrsetreg(&grf->soc_con2, mask, 233 enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) | 234 disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT : 235 UPCTL0_BST_DIABLE_SHIFT) | 236 enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT : 237 UPCTL0_LPDDR3_ODT_EN_SHIFT)); 238 } 239 240 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, 241 struct rk3288_sdram_params *sdram_params, 242 struct rk3288_grf *grf) 243 { 244 unsigned int burstlen; 245 246 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; 247 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, 248 sizeof(sdram_params->pctl_timing)); 249 switch (sdram_params->base.dramtype) { 250 case LPDDR3: 251 writel(sdram_params->pctl_timing.tcl - 1, 252 &pctl->dfitrddataen); 253 writel(sdram_params->pctl_timing.tcwl, 254 &pctl->dfitphywrlat); 255 burstlen >>= 1; 256 writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | 257 LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT | 258 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | 259 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, 260 &pctl->mcfg); 261 ddr_set_ddr3_mode(grf, channel, false); 262 ddr_set_enable(grf, channel, true); 263 ddr_set_en_bst_odt(grf, channel, true, false, 264 sdram_params->base.odt); 265 break; 266 case DDR3: 267 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { 268 writel(sdram_params->pctl_timing.tcl - 3, 269 &pctl->dfitrddataen); 270 } else { 271 writel(sdram_params->pctl_timing.tcl - 2, 272 &pctl->dfitrddataen); 273 } 274 writel(sdram_params->pctl_timing.tcwl - 1, 275 &pctl->dfitphywrlat); 276 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | 277 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | 278 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, 279 &pctl->mcfg); 280 ddr_set_ddr3_mode(grf, channel, true); 281 ddr_set_enable(grf, channel, true); 282 283 ddr_set_en_bst_odt(grf, channel, false, true, false); 284 break; 285 } 286 287 setbits_le32(&pctl->scfg, 1); 288 } 289 290 static void phy_cfg(const struct chan_info *chan, int channel, 291 struct rk3288_sdram_params *sdram_params) 292 { 293 struct rk3288_ddr_publ *publ = chan->publ; 294 struct rk3288_msch *msch = chan->msch; 295 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; 296 u32 dinit2, tmp; 297 int i; 298 299 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); 300 /* DDR PHY Timing */ 301 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, 302 sizeof(sdram_params->phy_timing)); 303 writel(sdram_params->base.noc_timing, &msch->ddrtiming); 304 writel(0x3f, &msch->readlatency); 305 writel(sdram_params->base.noc_activate, &msch->activate); 306 writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT | 307 1 << BUSRDTORD_SHIFT, &msch->devtodev); 308 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | 309 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | 310 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); 311 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | 312 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, 313 &publ->ptr[1]); 314 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | 315 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, 316 &publ->ptr[2]); 317 318 switch (sdram_params->base.dramtype) { 319 case LPDDR3: 320 clrsetbits_le32(&publ->pgcr, 0x1F, 321 0 << PGCR_DFTLMT_SHIFT | 322 0 << PGCR_DFTCMP_SHIFT | 323 1 << PGCR_DQSCFG_SHIFT | 324 0 << PGCR_ITMDMD_SHIFT); 325 /* DDRMODE select LPDDR3 */ 326 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, 327 DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT); 328 clrsetbits_le32(&publ->dxccr, 329 DQSNRES_MASK << DQSNRES_SHIFT | 330 DQSRES_MASK << DQSRES_SHIFT, 331 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT); 332 tmp = readl(&publ->dtpr[1]); 333 tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) - 334 ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK); 335 clrsetbits_le32(&publ->dsgcr, 336 DQSGE_MASK << DQSGE_SHIFT | 337 DQSGX_MASK << DQSGX_SHIFT, 338 tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT); 339 break; 340 case DDR3: 341 clrbits_le32(&publ->pgcr, 0x1f); 342 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, 343 DDRMD_DDR3 << DDRMD_SHIFT); 344 break; 345 } 346 if (sdram_params->base.odt) { 347 /*dynamic RTT enable */ 348 for (i = 0; i < 4; i++) 349 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); 350 } else { 351 /*dynamic RTT disable */ 352 for (i = 0; i < 4; i++) 353 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); 354 } 355 } 356 357 static void phy_init(struct rk3288_ddr_publ *publ) 358 { 359 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST 360 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); 361 udelay(1); 362 while ((readl(&publ->pgsr) & 363 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != 364 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) 365 ; 366 } 367 368 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, 369 u32 cmd, u32 arg) 370 { 371 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); 372 udelay(1); 373 while (readl(&pctl->mcmd) & START_CMD) 374 ; 375 } 376 377 static inline void send_command_op(struct rk3288_ddr_pctl *pctl, 378 u32 rank, u32 cmd, u32 ma, u32 op) 379 { 380 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | 381 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); 382 } 383 384 static void memory_init(struct rk3288_ddr_publ *publ, 385 u32 dramtype) 386 { 387 setbits_le32(&publ->pir, 388 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP 389 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC 390 | (dramtype == DDR3 ? PIR_DRAMRST : 0))); 391 udelay(1); 392 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) 393 != (PGSR_IDONE | PGSR_DLDONE)) 394 ; 395 } 396 397 static void move_to_config_state(struct rk3288_ddr_publ *publ, 398 struct rk3288_ddr_pctl *pctl) 399 { 400 unsigned int state; 401 402 while (1) { 403 state = readl(&pctl->stat) & PCTL_STAT_MSK; 404 405 switch (state) { 406 case LOW_POWER: 407 writel(WAKEUP_STATE, &pctl->sctl); 408 while ((readl(&pctl->stat) & PCTL_STAT_MSK) 409 != ACCESS) 410 ; 411 /* wait DLL lock */ 412 while ((readl(&publ->pgsr) & PGSR_DLDONE) 413 != PGSR_DLDONE) 414 ; 415 /* 416 * if at low power state,need wakeup first, 417 * and then enter the config 418 * so here no break. 419 */ 420 case ACCESS: 421 /* no break */ 422 case INIT_MEM: 423 writel(CFG_STATE, &pctl->sctl); 424 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 425 ; 426 break; 427 case CONFIG: 428 return; 429 default: 430 break; 431 } 432 } 433 } 434 435 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, 436 u32 n, struct rk3288_grf *grf) 437 { 438 struct rk3288_ddr_pctl *pctl = chan->pctl; 439 struct rk3288_ddr_publ *publ = chan->publ; 440 struct rk3288_msch *msch = chan->msch; 441 442 if (n == 1) { 443 setbits_le32(&pctl->ppcfg, 1); 444 rk_setreg(&grf->soc_con0, 1 << (8 + channel)); 445 setbits_le32(&msch->ddrtiming, 1 << 31); 446 /* Data Byte disable*/ 447 clrbits_le32(&publ->datx8[2].dxgcr, 1); 448 clrbits_le32(&publ->datx8[3].dxgcr, 1); 449 /* disable DLL */ 450 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); 451 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); 452 } else { 453 clrbits_le32(&pctl->ppcfg, 1); 454 rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); 455 clrbits_le32(&msch->ddrtiming, 1 << 31); 456 /* Data Byte enable*/ 457 setbits_le32(&publ->datx8[2].dxgcr, 1); 458 setbits_le32(&publ->datx8[3].dxgcr, 1); 459 460 /* enable DLL */ 461 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); 462 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); 463 /* reset DLL */ 464 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); 465 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); 466 udelay(10); 467 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); 468 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); 469 } 470 setbits_le32(&pctl->dfistcfg0, 1 << 2); 471 } 472 473 static int data_training(const struct chan_info *chan, int channel, 474 struct rk3288_sdram_params *sdram_params) 475 { 476 unsigned int j; 477 int ret = 0; 478 u32 rank; 479 int i; 480 u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; 481 struct rk3288_ddr_publ *publ = chan->publ; 482 struct rk3288_ddr_pctl *pctl = chan->pctl; 483 484 /* disable auto refresh */ 485 writel(0, &pctl->trefi); 486 487 if (sdram_params->base.dramtype != LPDDR3) 488 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); 489 rank = sdram_params->ch[channel].rank | 1; 490 for (j = 0; j < ARRAY_SIZE(step); j++) { 491 /* 492 * trigger QSTRN and RVTRN 493 * clear DTDONE status 494 */ 495 setbits_le32(&publ->pir, PIR_CLRSR); 496 497 /* trigger DTT */ 498 setbits_le32(&publ->pir, 499 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | 500 PIR_CLRSR); 501 udelay(1); 502 /* wait echo byte DTDONE */ 503 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) 504 != rank) 505 ; 506 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) 507 != rank) 508 ; 509 if (!(readl(&pctl->ppcfg) & 1)) { 510 while ((readl(&publ->datx8[2].dxgsr[0]) 511 & rank) != rank) 512 ; 513 while ((readl(&publ->datx8[3].dxgsr[0]) 514 & rank) != rank) 515 ; 516 } 517 if (readl(&publ->pgsr) & 518 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { 519 ret = -1; 520 break; 521 } 522 } 523 /* send some auto refresh to complement the lost while DTT */ 524 for (i = 0; i < (rank > 1 ? 8 : 4); i++) 525 send_command(pctl, rank, REF_CMD, 0); 526 527 if (sdram_params->base.dramtype != LPDDR3) 528 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); 529 530 /* resume auto refresh */ 531 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); 532 533 return ret; 534 } 535 536 static void move_to_access_state(const struct chan_info *chan) 537 { 538 struct rk3288_ddr_publ *publ = chan->publ; 539 struct rk3288_ddr_pctl *pctl = chan->pctl; 540 unsigned int state; 541 542 while (1) { 543 state = readl(&pctl->stat) & PCTL_STAT_MSK; 544 545 switch (state) { 546 case LOW_POWER: 547 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & 548 LP_TRIG_MASK) == 1) 549 return; 550 551 writel(WAKEUP_STATE, &pctl->sctl); 552 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 553 ; 554 /* wait DLL lock */ 555 while ((readl(&publ->pgsr) & PGSR_DLDONE) 556 != PGSR_DLDONE) 557 ; 558 break; 559 case INIT_MEM: 560 writel(CFG_STATE, &pctl->sctl); 561 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 562 ; 563 case CONFIG: 564 writel(GO_STATE, &pctl->sctl); 565 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) 566 ; 567 break; 568 case ACCESS: 569 return; 570 default: 571 break; 572 } 573 } 574 } 575 576 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, 577 struct rk3288_sdram_params *sdram_params) 578 { 579 struct rk3288_ddr_publ *publ = chan->publ; 580 581 if (sdram_params->ch[chnum].bk == 3) 582 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, 583 1 << PDQ_SHIFT); 584 else 585 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); 586 587 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); 588 } 589 590 static void dram_all_config(const struct dram_info *dram, 591 struct rk3288_sdram_params *sdram_params) 592 { 593 unsigned int chan; 594 u32 sys_reg = 0; 595 596 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; 597 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; 598 for (chan = 0; chan < sdram_params->num_channels; chan++) { 599 const struct rk3288_sdram_channel *info = 600 &sdram_params->ch[chan]; 601 602 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); 603 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); 604 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); 605 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); 606 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); 607 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); 608 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); 609 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); 610 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); 611 612 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); 613 } 614 writel(sys_reg, &dram->pmu->sys_reg[2]); 615 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); 616 } 617 618 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, 619 struct rk3288_sdram_params *sdram_params) 620 { 621 int reg; 622 int need_trainig = 0; 623 const struct chan_info *chan = &dram->chan[channel]; 624 struct rk3288_ddr_publ *publ = chan->publ; 625 626 if (data_training(chan, channel, sdram_params) < 0) { 627 reg = readl(&publ->datx8[0].dxgsr[0]); 628 /* Check the result for rank 0 */ 629 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { 630 debug("data training fail!\n"); 631 return -EIO; 632 } else if ((channel == 1) && 633 (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { 634 sdram_params->num_channels = 1; 635 } 636 637 /* Check the result for rank 1 */ 638 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { 639 sdram_params->ch[channel].rank = 1; 640 clrsetbits_le32(&publ->pgcr, 0xF << 18, 641 sdram_params->ch[channel].rank << 18); 642 need_trainig = 1; 643 } 644 reg = readl(&publ->datx8[2].dxgsr[0]); 645 if (reg & (1 << 4)) { 646 sdram_params->ch[channel].bw = 1; 647 set_bandwidth_ratio(chan, channel, 648 sdram_params->ch[channel].bw, 649 dram->grf); 650 need_trainig = 1; 651 } 652 } 653 /* Assume the Die bit width are the same with the chip bit width */ 654 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; 655 656 if (need_trainig && 657 (data_training(chan, channel, sdram_params) < 0)) { 658 if (sdram_params->base.dramtype == LPDDR3) { 659 ddr_phy_ctl_reset(dram->cru, channel, 1); 660 udelay(10); 661 ddr_phy_ctl_reset(dram->cru, channel, 0); 662 udelay(10); 663 } 664 debug("2nd data training failed!"); 665 return -EIO; 666 } 667 668 return 0; 669 } 670 671 static int sdram_col_row_detect(struct dram_info *dram, int channel, 672 struct rk3288_sdram_params *sdram_params) 673 { 674 int row, col; 675 unsigned int addr; 676 const struct chan_info *chan = &dram->chan[channel]; 677 struct rk3288_ddr_pctl *pctl = chan->pctl; 678 struct rk3288_ddr_publ *publ = chan->publ; 679 int ret = 0; 680 681 /* Detect col */ 682 for (col = 11; col >= 9; col--) { 683 writel(0, CONFIG_SYS_SDRAM_BASE); 684 addr = CONFIG_SYS_SDRAM_BASE + 685 (1 << (col + sdram_params->ch[channel].bw - 1)); 686 writel(TEST_PATTEN, addr); 687 if ((readl(addr) == TEST_PATTEN) && 688 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 689 break; 690 } 691 if (col == 8) { 692 printf("Col detect error\n"); 693 ret = -EINVAL; 694 goto out; 695 } else { 696 sdram_params->ch[channel].col = col; 697 } 698 699 move_to_config_state(publ, pctl); 700 writel(4, &chan->msch->ddrconf); 701 move_to_access_state(chan); 702 /* Detect row*/ 703 for (row = 16; row >= 12; row--) { 704 writel(0, CONFIG_SYS_SDRAM_BASE); 705 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); 706 writel(TEST_PATTEN, addr); 707 if ((readl(addr) == TEST_PATTEN) && 708 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 709 break; 710 } 711 if (row == 11) { 712 printf("Row detect error\n"); 713 ret = -EINVAL; 714 } else { 715 sdram_params->ch[channel].cs1_row = row; 716 sdram_params->ch[channel].row_3_4 = 0; 717 debug("chn %d col %d, row %d\n", channel, col, row); 718 sdram_params->ch[channel].cs0_row = row; 719 } 720 721 out: 722 return ret; 723 } 724 725 static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params) 726 { 727 int i, tmp, size, ret = 0; 728 729 tmp = sdram_params->ch[0].col - 9; 730 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; 731 tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); 732 size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); 733 for (i = 0; i < size; i++) 734 if (tmp == ddrconf_table[i]) 735 break; 736 if (i >= size) { 737 printf("niu config not found\n"); 738 ret = -EINVAL; 739 } else { 740 sdram_params->base.ddrconfig = i; 741 } 742 743 return ret; 744 } 745 746 static int sdram_get_stride(struct rk3288_sdram_params *sdram_params) 747 { 748 int stride = -1; 749 int ret = 0; 750 long cap = sdram_params->num_channels * (1u << 751 (sdram_params->ch[0].cs0_row + 752 sdram_params->ch[0].col + 753 (sdram_params->ch[0].rank - 1) + 754 sdram_params->ch[0].bw + 755 3 - 20)); 756 757 switch (cap) { 758 case 512: 759 stride = 0; 760 break; 761 case 1024: 762 stride = 5; 763 break; 764 case 2048: 765 stride = 9; 766 break; 767 case 4096: 768 stride = 0xd; 769 break; 770 default: 771 stride = -1; 772 printf("could not find correct stride, cap error!\n"); 773 ret = -EINVAL; 774 break; 775 } 776 sdram_params->base.stride = stride; 777 778 return ret; 779 } 780 781 static int sdram_init(struct dram_info *dram, 782 struct rk3288_sdram_params *sdram_params) 783 { 784 int channel; 785 int zqcr; 786 int ret; 787 788 debug("%s start\n", __func__); 789 if ((sdram_params->base.dramtype == DDR3 && 790 sdram_params->base.ddr_freq > 800000000) || 791 (sdram_params->base.dramtype == LPDDR3 && 792 sdram_params->base.ddr_freq > 533000000)) { 793 debug("SDRAM frequency is too high!"); 794 return -E2BIG; 795 } 796 797 debug("ddr clk dpll\n"); 798 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); 799 debug("ret=%d\n", ret); 800 if (ret) { 801 debug("Could not set DDR clock\n"); 802 return ret; 803 } 804 805 for (channel = 0; channel < 2; channel++) { 806 const struct chan_info *chan = &dram->chan[channel]; 807 struct rk3288_ddr_pctl *pctl = chan->pctl; 808 struct rk3288_ddr_publ *publ = chan->publ; 809 810 /* map all the 4GB space to the current channel */ 811 if (channel) 812 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17); 813 else 814 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a); 815 phy_pctrl_reset(dram->cru, publ, channel); 816 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); 817 818 dfi_cfg(pctl, sdram_params->base.dramtype); 819 820 pctl_cfg(channel, pctl, sdram_params, dram->grf); 821 822 phy_cfg(chan, channel, sdram_params); 823 824 phy_init(publ); 825 826 writel(POWER_UP_START, &pctl->powctl); 827 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) 828 ; 829 830 memory_init(publ, sdram_params->base.dramtype); 831 move_to_config_state(publ, pctl); 832 833 if (sdram_params->base.dramtype == LPDDR3) { 834 send_command(pctl, 3, DESELECT_CMD, 0); 835 udelay(1); 836 send_command(pctl, 3, PREA_CMD, 0); 837 udelay(1); 838 send_command_op(pctl, 3, MRS_CMD, 63, 0xfc); 839 udelay(1); 840 send_command_op(pctl, 3, MRS_CMD, 1, 841 sdram_params->phy_timing.mr[1]); 842 udelay(1); 843 send_command_op(pctl, 3, MRS_CMD, 2, 844 sdram_params->phy_timing.mr[2]); 845 udelay(1); 846 send_command_op(pctl, 3, MRS_CMD, 3, 847 sdram_params->phy_timing.mr[3]); 848 udelay(1); 849 } 850 851 /* Using 32bit bus width for detect */ 852 sdram_params->ch[channel].bw = 2; 853 set_bandwidth_ratio(chan, channel, 854 sdram_params->ch[channel].bw, dram->grf); 855 /* 856 * set cs, using n=3 for detect 857 * CS0, n=1 858 * CS1, n=2 859 * CS0 & CS1, n = 3 860 */ 861 sdram_params->ch[channel].rank = 2, 862 clrsetbits_le32(&publ->pgcr, 0xF << 18, 863 (sdram_params->ch[channel].rank | 1) << 18); 864 865 /* DS=40ohm,ODT=155ohm */ 866 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | 867 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | 868 0x19 << PD_OUTPUT_SHIFT; 869 writel(zqcr, &publ->zq1cr[0]); 870 writel(zqcr, &publ->zq0cr[0]); 871 872 if (sdram_params->base.dramtype == LPDDR3) { 873 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 874 udelay(10); 875 send_command_op(pctl, 876 sdram_params->ch[channel].rank | 1, 877 MRS_CMD, 11, 878 sdram_params->base.odt ? 3 : 0); 879 if (channel == 0) { 880 writel(0, &pctl->mrrcfg0); 881 send_command_op(pctl, 1, MRR_CMD, 8, 0); 882 /* S8 */ 883 if ((readl(&pctl->mrrstat0) & 0x3) != 3) { 884 debug("failed!"); 885 return -EREMOTEIO; 886 } 887 } 888 } 889 890 /* Detect the rank and bit-width with data-training */ 891 sdram_rank_bw_detect(dram, channel, sdram_params); 892 893 if (sdram_params->base.dramtype == LPDDR3) { 894 u32 i; 895 writel(0, &pctl->mrrcfg0); 896 for (i = 0; i < 17; i++) 897 send_command_op(pctl, 1, MRR_CMD, i, 0); 898 } 899 writel(15, &chan->msch->ddrconf); 900 move_to_access_state(chan); 901 /* DDR3 and LPDDR3 are always 8 bank, no need detect */ 902 sdram_params->ch[channel].bk = 3; 903 /* Detect Col and Row number*/ 904 ret = sdram_col_row_detect(dram, channel, sdram_params); 905 if (ret) 906 goto error; 907 } 908 /* Find NIU DDR configuration */ 909 ret = sdram_get_niu_config(sdram_params); 910 if (ret) 911 goto error; 912 /* Find stride setting */ 913 ret = sdram_get_stride(sdram_params); 914 if (ret) 915 goto error; 916 917 dram_all_config(dram, sdram_params); 918 debug("%s done\n", __func__); 919 920 return 0; 921 error: 922 printf("DRAM init failed!\n"); 923 hang(); 924 } 925 926 # ifdef CONFIG_ROCKCHIP_FAST_SPL 927 static int veyron_init(struct dram_info *priv) 928 { 929 struct udevice *pmic; 930 int ret; 931 932 ret = uclass_first_device_err(UCLASS_PMIC, &pmic); 933 if (ret) 934 return ret; 935 936 /* Slowly raise to max CPU voltage to prevent overshoot */ 937 ret = rk8xx_spl_configure_buck(pmic, 1, 1200000); 938 if (ret) 939 return ret; 940 udelay(175);/* Must wait for voltage to stabilize, 2mV/us */ 941 ret = rk8xx_spl_configure_buck(pmic, 1, 1400000); 942 if (ret) 943 return ret; 944 udelay(100);/* Must wait for voltage to stabilize, 2mV/us */ 945 946 rk3288_clk_configure_cpu(priv->cru, priv->grf); 947 948 return 0; 949 } 950 # endif 951 952 static int setup_sdram(struct udevice *dev) 953 { 954 struct dram_info *priv = dev_get_priv(dev); 955 struct rk3288_sdram_params *params = dev_get_platdata(dev); 956 957 # ifdef CONFIG_ROCKCHIP_FAST_SPL 958 if (priv->is_veyron) { 959 int ret; 960 961 ret = veyron_init(priv); 962 if (ret) 963 return ret; 964 } 965 # endif 966 967 return sdram_init(priv, params); 968 } 969 970 static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev) 971 { 972 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 973 struct rk3288_sdram_params *params = dev_get_platdata(dev); 974 int ret; 975 976 /* Rk3288 supports dual-channel, set default channel num to 2 */ 977 params->num_channels = 2; 978 ret = dev_read_u32_array(dev, "rockchip,pctl-timing", 979 (u32 *)¶ms->pctl_timing, 980 sizeof(params->pctl_timing) / sizeof(u32)); 981 if (ret) { 982 debug("%s: Cannot read rockchip,pctl-timing\n", __func__); 983 return -EINVAL; 984 } 985 ret = dev_read_u32_array(dev, "rockchip,phy-timing", 986 (u32 *)¶ms->phy_timing, 987 sizeof(params->phy_timing) / sizeof(u32)); 988 if (ret) { 989 debug("%s: Cannot read rockchip,phy-timing\n", __func__); 990 return -EINVAL; 991 } 992 ret = dev_read_u32_array(dev, "rockchip,sdram-params", 993 (u32 *)¶ms->base, 994 sizeof(params->base) / sizeof(u32)); 995 if (ret) { 996 debug("%s: Cannot read rockchip,sdram-params\n", __func__); 997 return -EINVAL; 998 } 999 #ifdef CONFIG_ROCKCHIP_FAST_SPL 1000 struct dram_info *priv = dev_get_priv(dev); 1001 1002 priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron"); 1003 #endif 1004 ret = regmap_init_mem(dev, ¶ms->map); 1005 if (ret) 1006 return ret; 1007 #endif 1008 1009 return 0; 1010 } 1011 #endif /* CONFIG_SPL_BUILD */ 1012 1013 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1014 static int conv_of_platdata(struct udevice *dev) 1015 { 1016 struct rk3288_sdram_params *plat = dev_get_platdata(dev); 1017 struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat; 1018 int ret; 1019 1020 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, 1021 sizeof(plat->pctl_timing)); 1022 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, 1023 sizeof(plat->phy_timing)); 1024 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); 1025 /* Rk3288 supports dual-channel, set default channel num to 2 */ 1026 plat->num_channels = 2; 1027 ret = regmap_init_mem_platdata(dev, of_plat->reg, 1028 ARRAY_SIZE(of_plat->reg) / 2, 1029 &plat->map); 1030 if (ret) 1031 return ret; 1032 1033 return 0; 1034 } 1035 #endif 1036 1037 static int rk3288_dmc_probe(struct udevice *dev) 1038 { 1039 #ifdef CONFIG_SPL_BUILD 1040 struct rk3288_sdram_params *plat = dev_get_platdata(dev); 1041 struct udevice *dev_clk; 1042 struct regmap *map; 1043 int ret; 1044 #endif 1045 struct dram_info *priv = dev_get_priv(dev); 1046 1047 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 1048 #ifdef CONFIG_SPL_BUILD 1049 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1050 ret = conv_of_platdata(dev); 1051 if (ret) 1052 return ret; 1053 #endif 1054 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); 1055 if (IS_ERR(map)) 1056 return PTR_ERR(map); 1057 priv->chan[0].msch = regmap_get_range(map, 0); 1058 priv->chan[1].msch = (struct rk3288_msch *) 1059 (regmap_get_range(map, 0) + 0x80); 1060 1061 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1062 priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); 1063 1064 priv->chan[0].pctl = regmap_get_range(plat->map, 0); 1065 priv->chan[0].publ = regmap_get_range(plat->map, 1); 1066 priv->chan[1].pctl = regmap_get_range(plat->map, 2); 1067 priv->chan[1].publ = regmap_get_range(plat->map, 3); 1068 1069 ret = rockchip_get_clk(&dev_clk); 1070 if (ret) 1071 return ret; 1072 priv->ddr_clk.id = CLK_DDR; 1073 ret = clk_request(dev_clk, &priv->ddr_clk); 1074 if (ret) 1075 return ret; 1076 1077 priv->cru = rockchip_get_cru(); 1078 if (IS_ERR(priv->cru)) 1079 return PTR_ERR(priv->cru); 1080 ret = setup_sdram(dev); 1081 if (ret) 1082 return ret; 1083 #else 1084 priv->info.base = CONFIG_SYS_SDRAM_BASE; 1085 priv->info.size = rockchip_sdram_size( 1086 (phys_addr_t)&priv->pmu->sys_reg[2]); 1087 #endif 1088 1089 return 0; 1090 } 1091 1092 static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info) 1093 { 1094 struct dram_info *priv = dev_get_priv(dev); 1095 1096 *info = priv->info; 1097 1098 return 0; 1099 } 1100 1101 static struct ram_ops rk3288_dmc_ops = { 1102 .get_info = rk3288_dmc_get_info, 1103 }; 1104 1105 static const struct udevice_id rk3288_dmc_ids[] = { 1106 { .compatible = "rockchip,rk3288-dmc" }, 1107 { } 1108 }; 1109 1110 U_BOOT_DRIVER(dmc_rk3288) = { 1111 .name = "rockchip_rk3288_dmc", 1112 .id = UCLASS_RAM, 1113 .of_match = rk3288_dmc_ids, 1114 .ops = &rk3288_dmc_ops, 1115 #ifdef CONFIG_SPL_BUILD 1116 .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata, 1117 #endif 1118 .probe = rk3288_dmc_probe, 1119 .priv_auto_alloc_size = sizeof(struct dram_info), 1120 #ifdef CONFIG_SPL_BUILD 1121 .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params), 1122 #endif 1123 }; 1124