| 88c3bb49 | 09-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Clean up ddr_setup()
Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register
ddr: socfpga: Clean up ddr_setup()
Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
show more ...
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| 8297dd1d | 09-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Clean up EMIF reset
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF
ddr: socfpga: Clean up EMIF reset
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
show more ...
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| ffd1e1a3 | 08-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Fix EMIF clear timeout
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simp
ddr: socfpga: Fix EMIF clear timeout
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.
This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
show more ...
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| dc3249b9 | 06-Mar-2019 |
Marek Vasut <marex@denx.de> |
ddr: socfpga: Fix newline in debug print on A10
The debug print is missing a newline, add it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguye
ddr: socfpga: Fix newline in debug print on A10
The debug print is missing a newline, add it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
show more ...
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| 07252f6f | 28-May-2018 |
Marek Vasut <marex@denx.de> |
ddr: altera: Add ECC DRAM scrubbing support for Arria10
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such
ddr: altera: Add ECC DRAM scrubbing support for Arria10
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
show more ...
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| e026b984 | 05-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Repair DQ window centering code
The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incor
ddr: altera: Repair DQ window centering code
The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
show more ...
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| 85f76628 | 05-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Staticize global variables
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.
Signed-off-by: Marek Vasut <
ddr: altera: Staticize global variables
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
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| ea9aa241 | 04-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Make DLEVEL behavior inclusive
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handlin
ddr: altera: Make DLEVEL behavior inclusive
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
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| 70ed80af | 04-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Zero DM IN delay in scc_mgr_zero_group()
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.
Signed-off-by: Marek Vasut
ddr: altera: Zero DM IN delay in scc_mgr_zero_group()
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
show more ...
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| f3f777cd | 04-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Remove unnecessary ODT mode config
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT
ddr: altera: Remove unnecessary ODT mode config
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
show more ...
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| f5f8c411 | 04-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Remove unnecessary update of the SCC
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manage
ddr: altera: Remove unnecessary update of the SCC
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
show more ...
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| 164eb23f | 04-Apr-2016 |
Marek Vasut <marex@denx.de> |
ddr: altera: Fix DRAM end value in protection rule
The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line
ddr: altera: Fix DRAM end value in protection rule
The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
show more ...
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