xref: /openbmc/u-boot/board/ti/ti816x/evm.c (revision d024236e5a31a2b4b82cbcc98b31b8170fc88d28)
1 /*
2  * evm.c
3  *
4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5  * Antoine Tenart, <atenart@adeneo-embedded.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <environment.h>
12 #include <spl.h>
13 #include <netdev.h>
14 #include <asm/cache.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mux.h>
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 int board_init(void)
28 {
29 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
30 #if defined(CONFIG_NAND)
31 	gpmc_init();
32 #endif
33 	return 0;
34 }
35 
36 int board_eth_init(bd_t *bis)
37 {
38 	uint8_t mac_addr[6];
39 	uint32_t mac_hi, mac_lo;
40 	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
41 
42 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
43 		printf("<ethaddr> not set. Reading from E-fuse\n");
44 		/* try reading mac address from efuse */
45 		mac_lo = readl(&cdev->macid0l);
46 		mac_hi = readl(&cdev->macid0h);
47 		mac_addr[0] = mac_hi & 0xFF;
48 		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
49 		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
50 		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
51 		mac_addr[4] = mac_lo & 0xFF;
52 		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
53 
54 		if (is_valid_ethaddr(mac_addr))
55 			eth_env_set_enetaddr("ethaddr", mac_addr);
56 		else
57 			printf("Unable to read MAC address. Set <ethaddr>\n");
58 	}
59 
60 	return davinci_emac_initialize();
61 }
62 
63 #ifdef CONFIG_SPL_BUILD
64 static struct module_pin_mux mmc_pin_mux[] = {
65 	{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
66 	{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
67 	{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
68 	{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
69 	{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
70 	{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
71 	{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
72 	{ -1 },
73 };
74 
75 void set_uart_mux_conf(void) {}
76 
77 void set_mux_conf_regs(void)
78 {
79 	configure_module_pin_mux(mmc_pin_mux);
80 }
81 
82 /*
83  * EMIF Paramters.  Refer the EMIF register documentation and the
84  * memory datasheet for details.  This is for 796 MHz.
85  */
86 #define EMIF_TIM1   0x1779C9FE
87 #define EMIF_TIM2   0x50608074
88 #define EMIF_TIM3   0x009F857F
89 #define EMIF_SDREF  0x10001841
90 #define EMIF_SDCFG  0x62A73832
91 #define EMIF_PHYCFG 0x00000110
92 static const struct emif_regs ddr3_emif_regs = {
93 	.sdram_config		= EMIF_SDCFG,
94 	.ref_ctrl		= EMIF_SDREF,
95 	.sdram_tim1		= EMIF_TIM1,
96 	.sdram_tim2		= EMIF_TIM2,
97 	.sdram_tim3		= EMIF_TIM3,
98 	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
99 };
100 
101 static const struct cmd_control ddr3_ctrl = {
102 	.cmd0csratio	= 0x100,
103 	.cmd0iclkout	= 0x001,
104 	.cmd1csratio	= 0x100,
105 	.cmd1iclkout	= 0x001,
106 	.cmd2csratio	= 0x100,
107 	.cmd2iclkout	= 0x001,
108 };
109 
110 /* These values are obtained from the CCS app */
111 #define RD_DQS_GATE	(0x1B3)
112 #define RD_DQS		(0x35)
113 #define WR_DQS		(0x93)
114 static struct ddr_data ddr3_data = {
115 	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
116 	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
117 	.datawiratio0		= ((0x20<<10) | 0x20<<0),
118 	.datagiratio0		= ((0x20<<10) | 0x20<<0),
119 	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
120 	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
121 };
122 
123 static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
124 	.dmm_lisa_map_0 = 0x00000000,
125 	.dmm_lisa_map_1 = 0x00000000,
126 	.dmm_lisa_map_2 = 0x80640300,
127 	.dmm_lisa_map_3 = 0xC0640320,
128 };
129 
130 void sdram_init(void)
131 {
132 	/*
133 	 * Pass in our DDR3 config information and that we have 2 EMIFs to
134 	 * configure.
135 	 */
136 	config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
137 			&evm_lisa_map_regs, 2);
138 }
139 #endif /* CONFIG_SPL_BUILD */
140