fed0509c | 08-Feb-2018 |
Wenyou Yang <wenyou.yang@microchip.com> |
clk: at91: add PLLADIV driver
As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is
clk: at91: add PLLADIV driver
As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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63a80b8d | 17-Nov-2017 |
Wenyou Yang <wenyou.yang@microchip.com> |
clk: at91: clk-generated: fix incorrect index of clk source
Differentiate the generic clock source selection value from the parent clock index to fix the incorrect assignment of the generic clock so
clk: at91: clk-generated: fix incorrect index of clk source
Differentiate the generic clock source selection value from the parent clock index to fix the incorrect assignment of the generic clock source selection.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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eb1ed2b1 | 17-Nov-2017 |
Ludovic Desroches <ludovic.desroches@microchip.com> |
clk: at91: clk-generated: select absolute closest rate
To get the same behavior as the Linux driver, instead of selecting the closest inferior rate, select the closest inferior or superior rate
Sig
clk: at91: clk-generated: select absolute closest rate
To get the same behavior as the Linux driver, instead of selecting the closest inferior rate, select the closest inferior or superior rate
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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3fea809b | 14-Apr-2017 |
Wenyou Yang <wenyou.yang@atmel.com> |
clk: at91: Align the at91 pmc's compatibles
Align the at91 pmc's compatibles with kernel.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by:
clk: at91: Align the at91 pmc's compatibles
Align the at91 pmc's compatibles with kernel.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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a9513d47 | 14-Apr-2017 |
Wenyou Yang <wenyou.yang@atmel.com> |
clk: at91: Align clk-master compatibles with kernel
Add the compatible "atmel,at91rm9200-clk-master" to align with the kernel.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon
clk: at91: Align clk-master compatibles with kernel
Add the compatible "atmel,at91rm9200-clk-master" to align with the kernel.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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6cadaa04 | 26-Sep-2016 |
Wenyou Yang <wenyou.yang@atmel.com> |
clk: at91: Improve the clock implementation
For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable th
clk: at91: Improve the clock implementation
For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable the spi0 peripheral clock, the .get_rate is to get the clock frequency.
The driver for periph32ck node is responsible for recursively binding its children as clk devices, not provide the clock ops.
So do the generated clock and system clock.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
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