1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Timesys Corporation 4 * Copyright (C) 2015 General Electric Company 5 * Copyright (C) 2014 Advantech 6 * Copyright (C) 2012 Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the GE MX6Q Bx50v3 boards. 9 */ 10 11 #ifndef __GE_BX50V3_CONFIG_H 12 #define __GE_BX50V3_CONFIG_H 13 14 #include <asm/arch/imx-regs.h> 15 #include <asm/mach-imx/gpio.h> 16 17 #define BX50V3_BOOTARGS_EXTRA 18 #if defined(CONFIG_TARGET_GE_B450V3) 19 #define CONFIG_BOARD_NAME "General Electric B450v3" 20 #elif defined(CONFIG_TARGET_GE_B650V3) 21 #define CONFIG_BOARD_NAME "General Electric B650v3" 22 #elif defined(CONFIG_TARGET_GE_B850V3) 23 #define CONFIG_BOARD_NAME "General Electric B850v3" 24 #undef BX50V3_BOOTARGS_EXTRA 25 #define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \ 26 "video=HDMI-A-1:1024x768@60 " 27 #else 28 #define CONFIG_BOARD_NAME "General Electric BA16 Generic" 29 #endif 30 31 #define CONFIG_MXC_UART_BASE UART3_BASE 32 #define CONSOLE_DEV "ttymxc2" 33 34 #define CONFIG_SUPPORT_EMMC_BOOT 35 36 37 #include "mx6_common.h" 38 #include <linux/sizes.h> 39 40 #define CONFIG_CMDLINE_TAG 41 #define CONFIG_SETUP_MEMORY_TAGS 42 #define CONFIG_INITRD_TAG 43 #define CONFIG_REVISION_TAG 44 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) 45 46 #define CONFIG_HW_WATCHDOG 47 #define CONFIG_IMX_WATCHDOG 48 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 49 50 #define CONFIG_MXC_UART 51 52 #define CONFIG_MXC_OCOTP 53 54 /* SATA Configs */ 55 #ifdef CONFIG_CMD_SATA 56 #define CONFIG_SYS_SATA_MAX_DEVICE 1 57 #define CONFIG_DWC_AHSATA_PORT_ID 0 58 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 59 #define CONFIG_LBA48 60 #endif 61 62 /* MMC Configs */ 63 #define CONFIG_FSL_USDHC 64 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 65 #define CONFIG_BOUNCE_BUFFER 66 67 /* USB Configs */ 68 #ifdef CONFIG_USB 69 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 70 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 71 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 72 #define CONFIG_MXC_USB_FLAGS 0 73 74 #define CONFIG_USBD_HS 75 #define CONFIG_USB_GADGET_MASS_STORAGE 76 #endif 77 78 /* Networking Configs */ 79 #ifdef CONFIG_NET 80 #define CONFIG_FEC_MXC 81 #define CONFIG_MII 82 #define IMX_FEC_BASE ENET_BASE_ADDR 83 #define CONFIG_FEC_XCV_TYPE RGMII 84 #define CONFIG_ETHPRIME "FEC" 85 #define CONFIG_FEC_MXC_PHYADDR 4 86 #define CONFIG_PHY_ATHEROS 87 #endif 88 89 /* Serial Flash */ 90 #ifdef CONFIG_CMD_SF 91 #define CONFIG_SF_DEFAULT_BUS 0 92 #define CONFIG_SF_DEFAULT_CS 0 93 #define CONFIG_SF_DEFAULT_SPEED 20000000 94 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 95 #endif 96 97 /* allow to overwrite serial and ethaddr */ 98 #define CONFIG_ENV_OVERWRITE 99 100 #define CONFIG_LOADADDR 0x12000000 101 102 #define CONFIG_EXTRA_ENV_SETTINGS \ 103 "bootcause=POR\0" \ 104 "bootlimit=10\0" \ 105 "image=/boot/fitImage\0" \ 106 "fdt_high=0xffffffff\0" \ 107 "dev=mmc\0" \ 108 "devnum=1\0" \ 109 "rootdev=mmcblk0p\0" \ 110 "quiet=quiet loglevel=0\0" \ 111 "console=" CONSOLE_DEV "\0" \ 112 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ 113 "ro rootwait cma=128M " \ 114 "bootcause=${bootcause} " \ 115 "${quiet} console=${console} ${rtc_status} " \ 116 BX50V3_BOOTARGS_EXTRA "\0" \ 117 "doquiet=" \ 118 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ 119 "then setenv quiet; fi\0" \ 120 "hasfirstboot=" \ 121 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ 122 "/boot/bootcause/firstboot\0" \ 123 "swappartitions=" \ 124 "setexpr partnum 3 - ${partnum}\0" \ 125 "failbootcmd=" \ 126 "bx50_backlight_enable; " \ 127 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ 128 "echo $msg; " \ 129 "setenv stdout vga; " \ 130 "echo \"\n\n\n\n \" $msg; " \ 131 "setenv stdout serial; " \ 132 "mw.b 0x7000A000 0xbc; " \ 133 "mw.b 0x7000A001 0x00; " \ 134 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ 135 "altbootcmd=" \ 136 "run doquiet; " \ 137 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 138 "run hasfirstboot || setenv partnum 0; " \ 139 "if test ${partnum} != 0; then " \ 140 "setenv bootcause REVERT; " \ 141 "run swappartitions loadimage doboot; " \ 142 "fi; " \ 143 "run failbootcmd\0" \ 144 "loadimage=" \ 145 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ 146 "doboot=" \ 147 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ 148 "run setargs; " \ 149 "bootm ${loadaddr}#conf@${confidx}\0" \ 150 "tryboot=" \ 151 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 152 "run loadimage || run swappartitions && run loadimage || " \ 153 "setenv partnum 0 && echo MISSING IMAGE;" \ 154 "run doboot; " \ 155 "run failbootcmd\0" \ 156 157 #define CONFIG_MMCBOOTCOMMAND \ 158 "if mmc dev ${devnum}; then " \ 159 "run doquiet; " \ 160 "run tryboot; " \ 161 "fi; " \ 162 163 #define CONFIG_USBBOOTCOMMAND \ 164 "echo Unsupported; " \ 165 166 #ifdef CONFIG_CMD_USB 167 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND 168 #else 169 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 170 #endif 171 172 #define CONFIG_ARP_TIMEOUT 200UL 173 174 /* Miscellaneous configurable options */ 175 176 #define CONFIG_SYS_MEMTEST_START 0x10000000 177 #define CONFIG_SYS_MEMTEST_END 0x10010000 178 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 179 180 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 181 182 /* Physical Memory Map */ 183 #define CONFIG_NR_DRAM_BANKS 1 184 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 185 186 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 187 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 188 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 189 190 #define CONFIG_SYS_INIT_SP_OFFSET \ 191 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 192 #define CONFIG_SYS_INIT_SP_ADDR \ 193 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 194 195 /* environment organization */ 196 #define CONFIG_ENV_SIZE (8 * 1024) 197 #define CONFIG_ENV_OFFSET (768 * 1024) 198 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 199 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 200 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 201 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 202 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 203 204 #ifndef CONFIG_SYS_DCACHE_OFF 205 #endif 206 207 #define CONFIG_SYS_FSL_USDHC_NUM 3 208 209 /* Framebuffer */ 210 #define CONFIG_VIDEO 211 #ifdef CONFIG_VIDEO 212 #define CONFIG_VIDEO_IPUV3 213 #define CONFIG_CFB_CONSOLE 214 #define CONFIG_VGA_AS_SINGLE_DEVICE 215 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF 216 #define CONFIG_SYS_CONSOLE_BG_COL 0x00 217 #define CONFIG_HIDE_LOGO_VERSION 218 #define CONFIG_IMX_HDMI 219 #define CONFIG_IMX_VIDEO_SKIP 220 #define CONFIG_CMD_BMP 221 #endif 222 223 #define CONFIG_PWM_IMX 224 #define CONFIG_IMX6_PWM_PER_CLK 66000000 225 226 #define CONFIG_PCI 227 #define CONFIG_PCI_PNP 228 #define CONFIG_PCI_SCAN_SHOW 229 #define CONFIG_PCIE_IMX 230 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 231 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) 232 233 #define CONFIG_RTC_RX8010SJ 234 #define CONFIG_SYS_RTC_BUS_NUM 2 235 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 236 237 /* I2C Configs */ 238 #define CONFIG_SYS_I2C 239 #define CONFIG_SYS_I2C_MXC 240 #define CONFIG_SYS_I2C_SPEED 100000 241 #define CONFIG_SYS_I2C_MXC_I2C1 242 #define CONFIG_SYS_I2C_MXC_I2C2 243 #define CONFIG_SYS_I2C_MXC_I2C3 244 245 #define CONFIG_SYS_NUM_I2C_BUSES 11 246 #define CONFIG_SYS_I2C_MAX_HOPS 1 247 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 248 {1, {I2C_NULL_HOP} }, \ 249 {2, {I2C_NULL_HOP} }, \ 250 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ 251 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 252 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 253 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ 254 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ 255 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ 256 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ 257 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ 258 } 259 260 #define CONFIG_BCH 261 262 #endif /* __GE_BX50V3_CONFIG_H */ 263