1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 */
7
8 #include <common.h>
9 #include <pci.h>
10 #include <asm/processor.h>
11 #include <asm/mmu.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_pci.h>
14 #include <fsl_ddr_sdram.h>
15 #include <asm/fsl_serdes.h>
16 #include <spd_sdram.h>
17 #include <i2c.h>
18 #include <ioports.h>
19 #include <linux/libfdt.h>
20 #include <fdt_support.h>
21
22 #include "bcsr.h"
23
24 const qe_iop_conf_t qe_iop_conf_tab[] = {
25 /* GETH1 */
26 {4, 10, 1, 0, 2}, /* TxD0 */
27 {4, 9, 1, 0, 2}, /* TxD1 */
28 {4, 8, 1, 0, 2}, /* TxD2 */
29 {4, 7, 1, 0, 2}, /* TxD3 */
30 {4, 23, 1, 0, 2}, /* TxD4 */
31 {4, 22, 1, 0, 2}, /* TxD5 */
32 {4, 21, 1, 0, 2}, /* TxD6 */
33 {4, 20, 1, 0, 2}, /* TxD7 */
34 {4, 15, 2, 0, 2}, /* RxD0 */
35 {4, 14, 2, 0, 2}, /* RxD1 */
36 {4, 13, 2, 0, 2}, /* RxD2 */
37 {4, 12, 2, 0, 2}, /* RxD3 */
38 {4, 29, 2, 0, 2}, /* RxD4 */
39 {4, 28, 2, 0, 2}, /* RxD5 */
40 {4, 27, 2, 0, 2}, /* RxD6 */
41 {4, 26, 2, 0, 2}, /* RxD7 */
42 {4, 11, 1, 0, 2}, /* TX_EN */
43 {4, 24, 1, 0, 2}, /* TX_ER */
44 {4, 16, 2, 0, 2}, /* RX_DV */
45 {4, 30, 2, 0, 2}, /* RX_ER */
46 {4, 17, 2, 0, 2}, /* RX_CLK */
47 {4, 19, 1, 0, 2}, /* GTX_CLK */
48 {1, 31, 2, 0, 3}, /* GTX125 */
49
50 /* GETH2 */
51 {5, 10, 1, 0, 2}, /* TxD0 */
52 {5, 9, 1, 0, 2}, /* TxD1 */
53 {5, 8, 1, 0, 2}, /* TxD2 */
54 {5, 7, 1, 0, 2}, /* TxD3 */
55 {5, 23, 1, 0, 2}, /* TxD4 */
56 {5, 22, 1, 0, 2}, /* TxD5 */
57 {5, 21, 1, 0, 2}, /* TxD6 */
58 {5, 20, 1, 0, 2}, /* TxD7 */
59 {5, 15, 2, 0, 2}, /* RxD0 */
60 {5, 14, 2, 0, 2}, /* RxD1 */
61 {5, 13, 2, 0, 2}, /* RxD2 */
62 {5, 12, 2, 0, 2}, /* RxD3 */
63 {5, 29, 2, 0, 2}, /* RxD4 */
64 {5, 28, 2, 0, 2}, /* RxD5 */
65 {5, 27, 2, 0, 3}, /* RxD6 */
66 {5, 26, 2, 0, 2}, /* RxD7 */
67 {5, 11, 1, 0, 2}, /* TX_EN */
68 {5, 24, 1, 0, 2}, /* TX_ER */
69 {5, 16, 2, 0, 2}, /* RX_DV */
70 {5, 30, 2, 0, 2}, /* RX_ER */
71 {5, 17, 2, 0, 2}, /* RX_CLK */
72 {5, 19, 1, 0, 2}, /* GTX_CLK */
73 {1, 31, 2, 0, 3}, /* GTX125 */
74 {4, 6, 3, 0, 2}, /* MDIO */
75 {4, 5, 1, 0, 2}, /* MDC */
76
77 /* UART1 */
78 {2, 0, 1, 0, 2}, /* UART_SOUT1 */
79 {2, 1, 1, 0, 2}, /* UART_RTS1 */
80 {2, 2, 2, 0, 2}, /* UART_CTS1 */
81 {2, 3, 2, 0, 2}, /* UART_SIN1 */
82
83 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
84 };
85
86 void local_bus_init(void);
87
board_early_init_f(void)88 int board_early_init_f (void)
89 {
90 /*
91 * Initialize local bus.
92 */
93 local_bus_init ();
94
95 enable_8568mds_duart();
96 enable_8568mds_flash_write();
97 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
98 reset_8568mds_uccs();
99 #endif
100 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
101 enable_8568mds_qe_mdio();
102 #endif
103
104 #ifdef CONFIG_SYS_I2C2_OFFSET
105 /* Enable I2C2_SCL and I2C2_SDA */
106 volatile struct par_io *port_c;
107 port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
108 port_c->cpdir2 |= 0x0f000000;
109 port_c->cppar2 &= ~0x0f000000;
110 port_c->cppar2 |= 0x0a000000;
111 #endif
112
113 return 0;
114 }
115
checkboard(void)116 int checkboard (void)
117 {
118 printf ("Board: 8568 MDS\n");
119
120 return 0;
121 }
122
123 /*
124 * Initialize Local Bus
125 */
126 void
local_bus_init(void)127 local_bus_init(void)
128 {
129 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
130 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
131
132 uint clkdiv;
133 sys_info_t sysinfo;
134
135 get_sys_info(&sysinfo);
136 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
137
138 gur->lbiuiplldcr1 = 0x00078080;
139 if (clkdiv == 16) {
140 gur->lbiuiplldcr0 = 0x7c0f1bf0;
141 } else if (clkdiv == 8) {
142 gur->lbiuiplldcr0 = 0x6c0f1bf0;
143 } else if (clkdiv == 4) {
144 gur->lbiuiplldcr0 = 0x5c0f1bf0;
145 }
146
147 lbc->lcrr |= 0x00030000;
148
149 asm("sync;isync;msync");
150 }
151
152 /*
153 * Initialize SDRAM memory on the Local Bus.
154 */
lbc_sdram_init(void)155 void lbc_sdram_init(void)
156 {
157 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
158
159 uint idx;
160 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
161 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
162 uint lsdmr_common;
163
164 puts("LBC SDRAM: ");
165 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
166 "\n ");
167
168 /*
169 * Setup SDRAM Base and Option Registers
170 */
171 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
172 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
173 asm("msync");
174
175 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
176 asm("msync");
177
178 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
179 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
180 asm("msync");
181
182 /*
183 * MPC8568 uses "new" 15-16 style addressing.
184 */
185 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
186 lsdmr_common |= LSDMR_BSMA1516;
187
188 /*
189 * Issue PRECHARGE ALL command.
190 */
191 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
192 asm("sync;msync");
193 *sdram_addr = 0xff;
194 ppcDcbf((unsigned long) sdram_addr);
195 udelay(100);
196
197 /*
198 * Issue 8 AUTO REFRESH commands.
199 */
200 for (idx = 0; idx < 8; idx++) {
201 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
202 asm("sync;msync");
203 *sdram_addr = 0xff;
204 ppcDcbf((unsigned long) sdram_addr);
205 udelay(100);
206 }
207
208 /*
209 * Issue 8 MODE-set command.
210 */
211 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
212 asm("sync;msync");
213 *sdram_addr = 0xff;
214 ppcDcbf((unsigned long) sdram_addr);
215 udelay(100);
216
217 /*
218 * Issue NORMAL OP command.
219 */
220 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
221 asm("sync;msync");
222 *sdram_addr = 0xff;
223 ppcDcbf((unsigned long) sdram_addr);
224 udelay(200); /* Overkill. Must wait > 200 bus cycles */
225
226 #endif /* enable SDRAM init */
227 }
228
229 #if defined(CONFIG_PCI)
230 #ifndef CONFIG_PCI_PNP
231 static struct pci_config_table pci_mpc8568mds_config_table[] = {
232 {
233 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
234 pci_cfgfunc_config_device,
235 {PCI_ENET0_IOADDR,
236 PCI_ENET0_MEMADDR,
237 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
238 },
239 {}
240 };
241 #endif
242
243 static struct pci_controller pci1_hose;
244 #endif /* CONFIG_PCI */
245
246 /*
247 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
248 */
249 void
pib_init(void)250 pib_init(void)
251 {
252 u8 val8, orig_i2c_bus;
253 /*
254 * Assign PIB PMC2/3 to PCI bus
255 */
256
257 /*switch temporarily to I2C bus #2 */
258 orig_i2c_bus = i2c_get_bus_num();
259 i2c_set_bus_num(1);
260
261 val8 = 0x00;
262 i2c_write(0x23, 0x6, 1, &val8, 1);
263 i2c_write(0x23, 0x7, 1, &val8, 1);
264 val8 = 0xff;
265 i2c_write(0x23, 0x2, 1, &val8, 1);
266 i2c_write(0x23, 0x3, 1, &val8, 1);
267
268 val8 = 0x00;
269 i2c_write(0x26, 0x6, 1, &val8, 1);
270 val8 = 0x34;
271 i2c_write(0x26, 0x7, 1, &val8, 1);
272 val8 = 0xf9;
273 i2c_write(0x26, 0x2, 1, &val8, 1);
274 val8 = 0xff;
275 i2c_write(0x26, 0x3, 1, &val8, 1);
276
277 val8 = 0x00;
278 i2c_write(0x27, 0x6, 1, &val8, 1);
279 i2c_write(0x27, 0x7, 1, &val8, 1);
280 val8 = 0xff;
281 i2c_write(0x27, 0x2, 1, &val8, 1);
282 val8 = 0xef;
283 i2c_write(0x27, 0x3, 1, &val8, 1);
284
285 asm("eieio");
286 i2c_set_bus_num(orig_i2c_bus);
287 }
288
289 #ifdef CONFIG_PCI
pci_init_board(void)290 void pci_init_board(void)
291 {
292 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
293 int first_free_busno = 0;
294 #ifdef CONFIG_PCI1
295 struct fsl_pci_info pci_info;
296 u32 devdisr, pordevsr, io_sel;
297 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
298
299 devdisr = in_be32(&gur->devdisr);
300 pordevsr = in_be32(&gur->pordevsr);
301 porpllsr = in_be32(&gur->porpllsr);
302 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
303
304 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
305
306 pci_speed = 66666000;
307 pci_32 = 1;
308 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
309 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
310
311 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
312 SET_STD_PCI_INFO(pci_info, 1);
313 set_next_law(pci_info.mem_phys,
314 law_size_bits(pci_info.mem_size), pci_info.law);
315 set_next_law(pci_info.io_phys,
316 law_size_bits(pci_info.io_size), pci_info.law);
317
318 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
319 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
320 (pci_32) ? 32 : 64,
321 (pci_speed == 33333000) ? "33" :
322 (pci_speed == 66666000) ? "66" : "unknown",
323 pci_clk_sel ? "sync" : "async",
324 pci_agent ? "agent" : "host",
325 pci_arb ? "arbiter" : "external-arbiter",
326 pci_info.regs);
327
328 #ifndef CONFIG_PCI_PNP
329 pci1_hose.config_table = pci_mpc8568mds_config_table;
330 #endif
331 first_free_busno = fsl_pci_init_port(&pci_info,
332 &pci1_hose, first_free_busno);
333 } else {
334 printf("PCI: disabled\n");
335 }
336
337 puts("\n");
338 #else
339 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
340 #endif
341
342 fsl_pcie_init_board(first_free_busno);
343 }
344 #endif /* CONFIG_PCI */
345
346 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)347 int ft_board_setup(void *blob, bd_t *bd)
348 {
349 ft_cpu_setup(blob, bd);
350
351 FT_FSL_PCI_SETUP;
352
353 return 0;
354 }
355 #endif
356