1 /* 2 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <linux/errno.h> 11 #include <asm/arch/fpga_manager.h> 12 #include <asm/arch/reset_manager.h> 13 #include <asm/arch/system_manager.h> 14 15 /* Timeout count */ 16 #define FPGA_TIMEOUT_CNT 0x1000000 17 18 static struct socfpga_fpga_manager *fpgamgr_regs = 19 (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; 20 21 int fpgamgr_dclkcnt_set(unsigned long cnt) 22 { 23 unsigned long i; 24 25 /* Clear any existing done status */ 26 if (readl(&fpgamgr_regs->dclkstat)) 27 writel(0x1, &fpgamgr_regs->dclkstat); 28 29 /* Write the dclkcnt */ 30 writel(cnt, &fpgamgr_regs->dclkcnt); 31 32 /* Wait till the dclkcnt done */ 33 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { 34 if (!readl(&fpgamgr_regs->dclkstat)) 35 continue; 36 37 writel(0x1, &fpgamgr_regs->dclkstat); 38 return 0; 39 } 40 41 return -ETIMEDOUT; 42 } 43 44 /* Write the RBF data to FPGA Manager */ 45 void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) 46 { 47 uint32_t src = (uint32_t)rbf_data; 48 uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; 49 50 /* Number of loops for 32-byte long copying. */ 51 uint32_t loops32 = rbf_size / 32; 52 /* Number of loops for 4-byte long copying + trailing bytes */ 53 uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); 54 55 asm volatile( 56 " cmp %2, #0\n" 57 " beq 2f\n" 58 "1: ldmia %0!, {r0-r7}\n" 59 " stmia %1!, {r0-r7}\n" 60 " sub %1, #32\n" 61 " subs %2, #1\n" 62 " bne 1b\n" 63 "2: cmp %3, #0\n" 64 " beq 4f\n" 65 "3: ldr %2, [%0], #4\n" 66 " str %2, [%1]\n" 67 " subs %3, #1\n" 68 " bne 3b\n" 69 "4: nop\n" 70 : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : 71 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); 72 } 73 74