1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_ENGINE_H_ 7 #define _DDR3_TRAINING_IP_ENGINE_H_ 8 9 #include "ddr3_training_ip_def.h" 10 #include "ddr3_training_ip_flow.h" 11 12 #define EDGE_1 0 13 #define EDGE_2 1 14 #define ALL_PUP_TRAINING 0xe 15 #define PUP_RESULT_EDGE_1_MASK 0xff 16 #define PUP_RESULT_EDGE_2_MASK (0xff << 8) 17 #define PUP_LOCK_RESULT_BIT 25 18 19 #define GET_TAP_RESULT(reg, edge) \ 20 (((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \ 21 (((reg) & PUP_RESULT_EDGE_2_MASK) >> 8)); 22 #define GET_LOCK_RESULT(reg) \ 23 (((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT) 24 25 #define EDGE_FAILURE 128 26 #define ALL_BITS_PER_PUP 128 27 28 #define MIN_WINDOW_SIZE 6 29 #define MAX_WINDOW_SIZE_RX 32 30 #define MAX_WINDOW_SIZE_TX 64 31 32 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type, 33 enum hws_search_dir search_dir, 34 enum hws_dir direction, 35 enum hws_edge_compare edge, 36 u32 init_val1, u32 init_val2, 37 u32 num_of_iterations, u32 start_pattern, 38 u32 end_pattern); 39 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern); 40 int ddr3_tip_load_pattern_to_mem_by_cpu(u32 dev_num, enum hws_pattern pattern, 41 u32 offset); 42 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num); 43 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, 44 enum hws_access_type pup_access_type, 45 u32 pup_num, u32 bit_num, 46 enum hws_search_dir search, 47 enum hws_dir direction, 48 enum hws_training_result result_type, 49 enum hws_training_load_op operation, 50 u32 cs_num_type, u32 **load_res, 51 int is_read_from_db, u8 cons_tap, 52 int is_check_result_validity); 53 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, 54 u32 interface_num, 55 enum hws_access_type pup_access_type, 56 u32 pup_num, enum hws_training_result result_type, 57 enum hws_control_element control_element, 58 enum hws_search_dir search_dir, enum hws_dir direction, 59 u32 interface_mask, u32 init_value, u32 num_iter, 60 enum hws_pattern pattern, 61 enum hws_edge_compare edge_comp, 62 enum hws_ddr_cs cs_type, u32 cs_num, 63 enum hws_training_ip_stat *train_status); 64 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, 65 u32 if_id, 66 enum hws_access_type pup_access_type, 67 u32 pup_num, 68 enum hws_training_result result_type, 69 enum hws_control_element control_element, 70 enum hws_search_dir search_dir, 71 enum hws_dir direction, 72 u32 interface_mask, u32 init_value1, 73 u32 init_value2, u32 num_iter, 74 enum hws_pattern pattern, 75 enum hws_edge_compare edge_comp, 76 enum hws_ddr_cs train_cs_type, u32 cs_num, 77 enum hws_training_ip_stat *train_status); 78 int is_odpg_access_done(u32 dev_num, u32 if_id); 79 void ddr3_tip_print_bist_res(void); 80 struct pattern_info *ddr3_tip_get_pattern_table(void); 81 u16 *ddr3_tip_get_mask_results_dq_reg(void); 82 u16 *ddr3_tip_get_mask_results_pup_reg_map(void); 83 84 #endif /* _DDR3_TRAINING_IP_ENGINE_H_ */ 85