1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/processor.h>
8 #include <asm/mmu.h>
9 #include <asm/cache.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/io.h>
12 #include <miiphy.h>
13 #include <linux/libfdt.h>
14 #include <fdt_support.h>
15 #include <fsl_mdio.h>
16 #include <tsec.h>
17 #include <mmc.h>
18 #include <netdev.h>
19 #include <pci.h>
20 #include <fsl_ifc.h>
21 #include <asm/fsl_pci.h>
22
23 #include "cpld.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
checkboard(void)27 int checkboard(void)
28 {
29 struct cpu_type *cpu = gd->arch.cpu;
30 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
31
32 printf("Board: %sPCIe, ", cpu->name);
33 printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
34
35 return 0;
36 }
37
board_early_init_f(void)38 int board_early_init_f(void)
39 {
40 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
41
42 /* Clock configuration to access CPLD using IFC(GPCM) */
43 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
44
45 return 0;
46 }
47
board_early_init_r(void)48 int board_early_init_r(void)
49 {
50 const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
51 int flash_esel = find_tlb_idx((void *)flashbase, 1);
52
53 /*
54 * Remap Boot flash region to caching-inhibited
55 * so that flash can be erased properly.
56 */
57
58 /* Flush d-cache and invalidate i-cache of any FLASH data */
59 flush_dcache();
60 invalidate_icache();
61
62 if (flash_esel == -1) {
63 /* very unlikely unless something is messed up */
64 puts("Error: Could not find TLB for FLASH BASE\n");
65 flash_esel = 1; /* give our best effort to continue */
66 } else {
67 /* invalidate existing TLB entry for flash */
68 disable_tlb(flash_esel);
69 }
70
71 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
72 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, flash_esel, BOOKE_PAGESZ_64M, 1);
74
75 return 0;
76 }
77
78 #ifdef CONFIG_PCI
pci_init_board(void)79 void pci_init_board(void)
80 {
81 fsl_pcie_init_board(0);
82 }
83 #endif /* ifdef CONFIG_PCI */
84
board_eth_init(bd_t * bis)85 int board_eth_init(bd_t *bis)
86 {
87 #ifdef CONFIG_TSEC_ENET
88 struct fsl_pq_mdio_info mdio_info;
89 struct tsec_info_struct tsec_info[2];
90 int num = 0;
91
92 #ifdef CONFIG_TSEC1
93 SET_STD_TSEC_INFO(tsec_info[num], 1);
94 num++;
95 #endif
96 #ifdef CONFIG_TSEC2
97 SET_STD_TSEC_INFO(tsec_info[num], 2);
98 num++;
99 #endif
100 if (!num) {
101 printf("No TSECs initialized\n");
102 return 0;
103 }
104
105 /* Register 1G MDIO bus */
106 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
107 mdio_info.name = DEFAULT_MII_NAME;
108
109 fsl_pq_mdio_init(bis, &mdio_info);
110
111 tsec_eth_init(bis, tsec_info, num);
112 #endif
113
114 return pci_eth_init(bis);
115 }
116
117 #if defined(CONFIG_OF_BOARD_SETUP)
fdt_del_sec(void * blob,int offset)118 void fdt_del_sec(void *blob, int offset)
119 {
120 int nodeoff = 0;
121
122 while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
123 CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
124 + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
125 fdt_del_node(blob, nodeoff);
126 offset++;
127 }
128 }
129
ft_board_setup(void * blob,bd_t * bd)130 int ft_board_setup(void *blob, bd_t *bd)
131 {
132 phys_addr_t base;
133 phys_size_t size;
134 struct cpu_type *cpu;
135
136 cpu = gd->arch.cpu;
137
138 ft_cpu_setup(blob, bd);
139
140 base = env_get_bootm_low();
141 size = env_get_bootm_size();
142
143 #if defined(CONFIG_PCI)
144 FT_FSL_PCI_SETUP;
145 #endif
146
147 fdt_fixup_memory(blob, (u64)base, (u64)size);
148 if (cpu->soc_ver == SVR_C291)
149 fdt_del_sec(blob, 1);
150 else if (cpu->soc_ver == SVR_C292)
151 fdt_del_sec(blob, 2);
152
153 return 0;
154 }
155 #endif
156