1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _XOR_H 7 #define _XOR_H 8 9 #define SRAM_BASE 0x40000000 10 11 #include "ddr3_hws_hw_training_def.h" 12 13 #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ 14 #define MV_XOR_MAX_CHAN 4 /* total channels for all units */ 15 #define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ 16 17 #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0)) 18 19 /* 20 * This structure describes address space window. Window base can be 21 * 64 bit, window size up to 4GB 22 */ 23 struct addr_win { 24 u32 base_low; /* 32bit base low */ 25 u32 base_high; /* 32bit base high */ 26 u32 size; /* 32bit size */ 27 }; 28 29 /* This structure describes SoC units address decode window */ 30 struct unit_win_info { 31 struct addr_win addr_win; /* An address window */ 32 int enable; /* Address decode window is enabled/disabled */ 33 u8 attrib; /* chip select attributes */ 34 u8 target_id; /* Target Id of this MV_TARGET */ 35 }; 36 37 /* 38 * This enumerator describes the type of functionality the XOR channel 39 * can have while using the same data structures. 40 */ 41 enum xor_type { 42 MV_XOR, /* XOR channel functions as XOR accelerator */ 43 MV_DMA, /* XOR channel functions as IDMA channel */ 44 MV_CRC32 /* XOR channel functions as CRC 32 calculator */ 45 }; 46 47 enum mv_state { 48 MV_IDLE, 49 MV_ACTIVE, 50 MV_PAUSED, 51 MV_UNDEFINED_STATE 52 }; 53 54 /* 55 * This enumerator describes the set of commands that can be applied on 56 * an engine (e.g. IDMA, XOR). Appling a comman depends on the current 57 * status (see MV_STATE enumerator) 58 * 59 * Start can be applied only when status is IDLE 60 * Stop can be applied only when status is IDLE, ACTIVE or PAUSED 61 * Pause can be applied only when status is ACTIVE 62 * Restart can be applied only when status is PAUSED 63 */ 64 enum mv_command { 65 MV_START, /* Start */ 66 MV_STOP, /* Stop */ 67 MV_PAUSE, /* Pause */ 68 MV_RESTART /* Restart */ 69 }; 70 71 enum xor_override_target { 72 SRC_ADDR0, /* Source Address #0 Control */ 73 SRC_ADDR1, /* Source Address #1 Control */ 74 SRC_ADDR2, /* Source Address #2 Control */ 75 SRC_ADDR3, /* Source Address #3 Control */ 76 SRC_ADDR4, /* Source Address #4 Control */ 77 SRC_ADDR5, /* Source Address #5 Control */ 78 SRC_ADDR6, /* Source Address #6 Control */ 79 SRC_ADDR7, /* Source Address #7 Control */ 80 XOR_DST_ADDR, /* Destination Address Control */ 81 XOR_NEXT_DESC /* Next Descriptor Address Control */ 82 }; 83 84 enum mv_state mv_xor_state_get(u32 chan); 85 void mv_xor_hal_init(u32 xor_chan_num); 86 int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl); 87 int mv_xor_command_set(u32 chan, enum mv_command command); 88 int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num, 89 int enable); 90 91 #endif 92