1 /* 2 * Copyright (C) 2016-2017 Intel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/io.h> 10 #include <dm.h> 11 #include <asm/arch/clock_manager.h> 12 13 static u32 eosc1_hz; 14 static u32 cb_intosc_hz; 15 static u32 f2s_free_hz; 16 static u32 cm_l4_main_clk_hz; 17 static u32 cm_l4_sp_clk_hz; 18 static u32 cm_l4_mp_clk_hz; 19 static u32 cm_l4_sys_free_clk_hz; 20 21 struct mainpll_cfg { 22 u32 vco0_psrc; 23 u32 vco1_denom; 24 u32 vco1_numer; 25 u32 mpuclk; 26 u32 mpuclk_cnt; 27 u32 mpuclk_src; 28 u32 nocclk; 29 u32 nocclk_cnt; 30 u32 nocclk_src; 31 u32 cntr2clk_cnt; 32 u32 cntr3clk_cnt; 33 u32 cntr4clk_cnt; 34 u32 cntr5clk_cnt; 35 u32 cntr6clk_cnt; 36 u32 cntr7clk_cnt; 37 u32 cntr7clk_src; 38 u32 cntr8clk_cnt; 39 u32 cntr9clk_cnt; 40 u32 cntr9clk_src; 41 u32 cntr15clk_cnt; 42 u32 nocdiv_l4mainclk; 43 u32 nocdiv_l4mpclk; 44 u32 nocdiv_l4spclk; 45 u32 nocdiv_csatclk; 46 u32 nocdiv_cstraceclk; 47 u32 nocdiv_cspdbclk; 48 }; 49 50 struct perpll_cfg { 51 u32 vco0_psrc; 52 u32 vco1_denom; 53 u32 vco1_numer; 54 u32 cntr2clk_cnt; 55 u32 cntr2clk_src; 56 u32 cntr3clk_cnt; 57 u32 cntr3clk_src; 58 u32 cntr4clk_cnt; 59 u32 cntr4clk_src; 60 u32 cntr5clk_cnt; 61 u32 cntr5clk_src; 62 u32 cntr6clk_cnt; 63 u32 cntr6clk_src; 64 u32 cntr7clk_cnt; 65 u32 cntr8clk_cnt; 66 u32 cntr8clk_src; 67 u32 cntr9clk_cnt; 68 u32 emacctl_emac0sel; 69 u32 emacctl_emac1sel; 70 u32 emacctl_emac2sel; 71 u32 gpiodiv_gpiodbclk; 72 }; 73 74 struct alteragrp_cfg { 75 u32 nocclk; 76 u32 mpuclk; 77 }; 78 79 static const struct socfpga_clock_manager *clock_manager_base = 80 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; 81 82 static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg) 83 { 84 if (fdtdec_get_int_array(blob, node, "altr,of_reg_value", 85 (u32 *)cfg, cfg_len)) { 86 /* could not find required property */ 87 return -EINVAL; 88 } 89 90 return 0; 91 } 92 93 static int of_get_input_clks(const void *blob, int node, u32 *val) 94 { 95 *val = fdtdec_get_uint(blob, node, "clock-frequency", 0); 96 if (!*val) 97 return -EINVAL; 98 99 return 0; 100 } 101 102 static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, 103 struct perpll_cfg *per_cfg, 104 struct alteragrp_cfg *altrgrp_cfg) 105 { 106 int node, child, len; 107 const char *node_name; 108 109 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK); 110 if (node < 0) 111 return -EINVAL; 112 113 child = fdt_first_subnode(blob, node); 114 if (child < 0) 115 return -EINVAL; 116 117 child = fdt_first_subnode(blob, child); 118 if (child < 0) 119 return -EINVAL; 120 121 node_name = fdt_get_name(blob, child, &len); 122 123 while (node_name) { 124 if (!strcmp(node_name, "osc1")) { 125 if (of_get_input_clks(blob, child, &eosc1_hz)) 126 return -EINVAL; 127 } else if (!strcmp(node_name, "cb_intosc_ls_clk")) { 128 if (of_get_input_clks(blob, child, &cb_intosc_hz)) 129 return -EINVAL; 130 } else if (!strcmp(node_name, "f2s_free_clk")) { 131 if (of_get_input_clks(blob, child, &f2s_free_hz)) 132 return -EINVAL; 133 } else if (!strcmp(node_name, "main_pll")) { 134 if (of_to_struct(blob, child, 135 sizeof(*main_cfg)/sizeof(u32), 136 main_cfg)) 137 return -EINVAL; 138 } else if (!strcmp(node_name, "periph_pll")) { 139 if (of_to_struct(blob, child, 140 sizeof(*per_cfg)/sizeof(u32), 141 per_cfg)) 142 return -EINVAL; 143 } else if (!strcmp(node_name, "altera")) { 144 if (of_to_struct(blob, child, 145 sizeof(*altrgrp_cfg)/sizeof(u32), 146 altrgrp_cfg)) 147 return -EINVAL; 148 149 main_cfg->mpuclk = altrgrp_cfg->mpuclk; 150 main_cfg->nocclk = altrgrp_cfg->nocclk; 151 } 152 child = fdt_next_subnode(blob, child); 153 154 if (child < 0) 155 break; 156 157 node_name = fdt_get_name(blob, child, &len); 158 } 159 160 return 0; 161 } 162 163 /* calculate the intended main VCO frequency based on handoff */ 164 static unsigned int cm_calc_handoff_main_vco_clk_hz 165 (struct mainpll_cfg *main_cfg) 166 { 167 unsigned int clk_hz; 168 169 /* Check main VCO clock source: eosc, intosc or f2s? */ 170 switch (main_cfg->vco0_psrc) { 171 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 172 clk_hz = eosc1_hz; 173 break; 174 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 175 clk_hz = cb_intosc_hz; 176 break; 177 case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 178 clk_hz = f2s_free_hz; 179 break; 180 default: 181 return 0; 182 } 183 184 /* calculate the VCO frequency */ 185 clk_hz /= 1 + main_cfg->vco1_denom; 186 clk_hz *= 1 + main_cfg->vco1_numer; 187 188 return clk_hz; 189 } 190 191 /* calculate the intended periph VCO frequency based on handoff */ 192 static unsigned int cm_calc_handoff_periph_vco_clk_hz( 193 struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 194 { 195 unsigned int clk_hz; 196 197 /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ 198 switch (per_cfg->vco0_psrc) { 199 case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 200 clk_hz = eosc1_hz; 201 break; 202 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 203 clk_hz = cb_intosc_hz; 204 break; 205 case CLKMGR_PERPLL_VCO0_PSRC_F2S: 206 clk_hz = f2s_free_hz; 207 break; 208 case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 209 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 210 clk_hz /= main_cfg->cntr15clk_cnt; 211 break; 212 default: 213 return 0; 214 } 215 216 /* calculate the VCO frequency */ 217 clk_hz /= 1 + per_cfg->vco1_denom; 218 clk_hz *= 1 + per_cfg->vco1_numer; 219 220 return clk_hz; 221 } 222 223 /* calculate the intended MPU clock frequency based on handoff */ 224 static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, 225 struct perpll_cfg *per_cfg) 226 { 227 unsigned int clk_hz; 228 229 /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 230 switch (main_cfg->mpuclk_src) { 231 case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 232 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 233 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) 234 + 1; 235 break; 236 case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 237 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 238 clk_hz /= ((main_cfg->mpuclk >> 239 CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 240 CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 241 break; 242 case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 243 clk_hz = eosc1_hz; 244 break; 245 case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 246 clk_hz = cb_intosc_hz; 247 break; 248 case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 249 clk_hz = f2s_free_hz; 250 break; 251 default: 252 return 0; 253 } 254 255 clk_hz /= main_cfg->mpuclk_cnt + 1; 256 return clk_hz; 257 } 258 259 /* calculate the intended NOC clock frequency based on handoff */ 260 static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, 261 struct perpll_cfg *per_cfg) 262 { 263 unsigned int clk_hz; 264 265 /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 266 switch (main_cfg->nocclk_src) { 267 case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: 268 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 269 clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) 270 + 1; 271 break; 272 case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: 273 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); 274 clk_hz /= ((main_cfg->nocclk >> 275 CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 276 CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; 277 break; 278 case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: 279 clk_hz = eosc1_hz; 280 break; 281 case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: 282 clk_hz = cb_intosc_hz; 283 break; 284 case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: 285 clk_hz = f2s_free_hz; 286 break; 287 default: 288 return 0; 289 } 290 291 clk_hz /= main_cfg->nocclk_cnt + 1; 292 return clk_hz; 293 } 294 295 /* return 1 if PLL ramp is required */ 296 static int cm_is_pll_ramp_required(int main0periph1, 297 struct mainpll_cfg *main_cfg, 298 struct perpll_cfg *per_cfg) 299 { 300 /* Check for main PLL */ 301 if (main0periph1 == 0) { 302 /* 303 * PLL ramp is not required if both MPU clock and NOC clock are 304 * not sourced from main PLL 305 */ 306 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 307 main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) 308 return 0; 309 310 /* 311 * PLL ramp is required if MPU clock is sourced from main PLL 312 * and MPU clock is over 900MHz (as advised by HW team) 313 */ 314 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && 315 (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 316 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 317 return 1; 318 319 /* 320 * PLL ramp is required if NOC clock is sourced from main PLL 321 * and NOC clock is over 300MHz (as advised by HW team) 322 */ 323 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && 324 (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 325 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 326 return 2; 327 328 } else if (main0periph1 == 1) { 329 /* 330 * PLL ramp is not required if both MPU clock and NOC clock are 331 * not sourced from periph PLL 332 */ 333 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 334 main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) 335 return 0; 336 337 /* 338 * PLL ramp is required if MPU clock are source from periph PLL 339 * and MPU clock is over 900MHz (as advised by HW team) 340 */ 341 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && 342 (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > 343 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) 344 return 1; 345 346 /* 347 * PLL ramp is required if NOC clock are source from periph PLL 348 * and NOC clock is over 300MHz (as advised by HW team) 349 */ 350 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && 351 (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > 352 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) 353 return 2; 354 } 355 356 return 0; 357 } 358 359 static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, 360 struct perpll_cfg *per_cfg, 361 u32 safe_hz, u32 clk_hz) 362 { 363 u32 cnt; 364 u32 clk; 365 u32 shift; 366 u32 mask; 367 u32 denom; 368 369 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 370 cnt = main_cfg->mpuclk_cnt; 371 clk = main_cfg->mpuclk; 372 shift = 0; 373 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 374 denom = main_cfg->vco1_denom; 375 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 376 cnt = main_cfg->nocclk_cnt; 377 clk = main_cfg->nocclk; 378 shift = 0; 379 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 380 denom = main_cfg->vco1_denom; 381 } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 382 cnt = main_cfg->mpuclk_cnt; 383 clk = main_cfg->mpuclk; 384 shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; 385 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; 386 denom = per_cfg->vco1_denom; 387 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 388 cnt = main_cfg->nocclk_cnt; 389 clk = main_cfg->nocclk; 390 shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; 391 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; 392 denom = per_cfg->vco1_denom; 393 } else { 394 return 0; 395 } 396 397 return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * 398 (1 + denom) - 1; 399 } 400 401 /* 402 * Calculate the new PLL numerator which is based on existing DTS hand off and 403 * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the 404 * numerator while maintaining denominator as denominator will influence the 405 * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final 406 * value for numerator is minus with 1 to cater our register value 407 * representation. 408 */ 409 static unsigned int cm_calc_safe_pll_numer(int main0periph1, 410 struct mainpll_cfg *main_cfg, 411 struct perpll_cfg *per_cfg, 412 unsigned int safe_hz) 413 { 414 unsigned int clk_hz = 0; 415 416 /* Check for main PLL */ 417 if (main0periph1 == 0) { 418 /* Check main VCO clock source: eosc, intosc or f2s? */ 419 switch (main_cfg->vco0_psrc) { 420 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: 421 clk_hz = eosc1_hz; 422 break; 423 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: 424 clk_hz = cb_intosc_hz; 425 break; 426 case CLKMGR_MAINPLL_VCO0_PSRC_F2S: 427 clk_hz = f2s_free_hz; 428 break; 429 default: 430 return 0; 431 } 432 } else if (main0periph1 == 1) { 433 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ 434 switch (per_cfg->vco0_psrc) { 435 case CLKMGR_PERPLL_VCO0_PSRC_EOSC: 436 clk_hz = eosc1_hz; 437 break; 438 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: 439 clk_hz = cb_intosc_hz; 440 break; 441 case CLKMGR_PERPLL_VCO0_PSRC_F2S: 442 clk_hz = f2s_free_hz; 443 break; 444 case CLKMGR_PERPLL_VCO0_PSRC_MAIN: 445 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); 446 clk_hz /= main_cfg->cntr15clk_cnt; 447 break; 448 default: 449 return 0; 450 } 451 } else { 452 return 0; 453 } 454 455 return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); 456 } 457 458 /* ramping the main PLL to final value */ 459 static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, 460 struct perpll_cfg *per_cfg, 461 unsigned int pll_ramp_main_hz) 462 { 463 unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 464 465 /* find out the increment value */ 466 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { 467 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 468 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 469 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { 470 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 471 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 472 } 473 474 /* execute the ramping here */ 475 for (clk_hz = pll_ramp_main_hz + clk_incr_hz; 476 clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 477 writel((main_cfg->vco1_denom << 478 CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 479 cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), 480 &clock_manager_base->main_pll.vco1); 481 mdelay(1); 482 cm_wait_for_lock(LOCKED_MASK); 483 } 484 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 485 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); 486 mdelay(1); 487 cm_wait_for_lock(LOCKED_MASK); 488 } 489 490 /* ramping the periph PLL to final value */ 491 static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, 492 struct perpll_cfg *per_cfg, 493 unsigned int pll_ramp_periph_hz) 494 { 495 unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; 496 497 /* find out the increment value */ 498 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { 499 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; 500 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); 501 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { 502 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; 503 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); 504 } 505 /* execute the ramping here */ 506 for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; 507 clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { 508 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 509 cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), 510 &clock_manager_base->per_pll.vco1); 511 mdelay(1); 512 cm_wait_for_lock(LOCKED_MASK); 513 } 514 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 515 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); 516 mdelay(1); 517 cm_wait_for_lock(LOCKED_MASK); 518 } 519 520 /* 521 * Setup clocks while making no assumptions of the 522 * previous state of the clocks. 523 * 524 * Start by being paranoid and gate all sw managed clocks 525 * 526 * Put all plls in bypass 527 * 528 * Put all plls VCO registers back to reset value (bgpwr dwn). 529 * 530 * Put peripheral and main pll src to reset value to avoid glitch. 531 * 532 * Delay 5 us. 533 * 534 * Deassert bg pwr dn and set numerator and denominator 535 * 536 * Start 7 us timer. 537 * 538 * set internal dividers 539 * 540 * Wait for 7 us timer. 541 * 542 * Enable plls 543 * 544 * Set external dividers while plls are locking 545 * 546 * Wait for pll lock 547 * 548 * Assert/deassert outreset all. 549 * 550 * Take all pll's out of bypass 551 * 552 * Clear safe mode 553 * 554 * set source main and peripheral clocks 555 * 556 * Ungate clocks 557 */ 558 559 static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) 560 { 561 unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, 562 ramp_required; 563 564 /* gate off all mainpll clock excpet HW managed clock */ 565 writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 566 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 567 &clock_manager_base->main_pll.enr); 568 569 /* now we can gate off the rest of the peripheral clocks */ 570 writel(0, &clock_manager_base->per_pll.en); 571 572 /* Put all plls in external bypass */ 573 writel(CLKMGR_MAINPLL_BYPASS_RESET, 574 &clock_manager_base->main_pll.bypasss); 575 writel(CLKMGR_PERPLL_BYPASS_RESET, 576 &clock_manager_base->per_pll.bypasss); 577 578 /* 579 * Put all plls VCO registers back to reset value. 580 * Some code might have messed with them. At same time set the 581 * desired clock source 582 */ 583 writel(CLKMGR_MAINPLL_VCO0_RESET | 584 CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | 585 (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), 586 &clock_manager_base->main_pll.vco0); 587 588 writel(CLKMGR_PERPLL_VCO0_RESET | 589 CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | 590 (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), 591 &clock_manager_base->per_pll.vco0); 592 593 writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); 594 writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); 595 596 /* clear the interrupt register status register */ 597 writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 598 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 599 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 600 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 601 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 602 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | 603 CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | 604 CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, 605 &clock_manager_base->intr); 606 607 /* Program VCO Numerator and Denominator for main PLL */ 608 ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); 609 if (ramp_required) { 610 /* set main PLL to safe starting threshold frequency */ 611 if (ramp_required == 1) 612 pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 613 else if (ramp_required == 2) 614 pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 615 616 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 617 cm_calc_safe_pll_numer(0, main_cfg, per_cfg, 618 pll_ramp_main_hz), 619 &clock_manager_base->main_pll.vco1); 620 } else 621 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | 622 main_cfg->vco1_numer, 623 &clock_manager_base->main_pll.vco1); 624 625 /* Program VCO Numerator and Denominator for periph PLL */ 626 ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); 627 if (ramp_required) { 628 /* set periph PLL to safe starting threshold frequency */ 629 if (ramp_required == 1) 630 pll_ramp_periph_hz = 631 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; 632 else if (ramp_required == 2) 633 pll_ramp_periph_hz = 634 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; 635 636 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 637 cm_calc_safe_pll_numer(1, main_cfg, per_cfg, 638 pll_ramp_periph_hz), 639 &clock_manager_base->per_pll.vco1); 640 } else 641 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | 642 per_cfg->vco1_numer, 643 &clock_manager_base->per_pll.vco1); 644 645 /* Wait for at least 5 us */ 646 udelay(5); 647 648 /* Now deassert BGPWRDN and PWRDN */ 649 clrbits_le32(&clock_manager_base->main_pll.vco0, 650 CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | 651 CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); 652 clrbits_le32(&clock_manager_base->per_pll.vco0, 653 CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | 654 CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); 655 656 /* Wait for at least 7 us */ 657 udelay(7); 658 659 /* enable the VCO and disable the external regulator to PLL */ 660 writel((readl(&clock_manager_base->main_pll.vco0) & 661 ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | 662 CLKMGR_MAINPLL_VCO0_EN_SET_MSK, 663 &clock_manager_base->main_pll.vco0); 664 writel((readl(&clock_manager_base->per_pll.vco0) & 665 ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | 666 CLKMGR_PERPLL_VCO0_EN_SET_MSK, 667 &clock_manager_base->per_pll.vco0); 668 669 /* setup all the main PLL counter and clock source */ 670 writel(main_cfg->nocclk, 671 SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); 672 writel(main_cfg->mpuclk, 673 SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); 674 675 /* main_emaca_clk divider */ 676 writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); 677 /* main_emacb_clk divider */ 678 writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); 679 /* main_emac_ptp_clk divider */ 680 writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); 681 /* main_gpio_db_clk divider */ 682 writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); 683 /* main_sdmmc_clk divider */ 684 writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); 685 /* main_s2f_user0_clk divider */ 686 writel(main_cfg->cntr7clk_cnt | 687 (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), 688 &clock_manager_base->main_pll.cntr7clk); 689 /* main_s2f_user1_clk divider */ 690 writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); 691 /* main_hmc_pll_clk divider */ 692 writel(main_cfg->cntr9clk_cnt | 693 (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), 694 &clock_manager_base->main_pll.cntr9clk); 695 /* main_periph_ref_clk divider */ 696 writel(main_cfg->cntr15clk_cnt, 697 &clock_manager_base->main_pll.cntr15clk); 698 699 /* setup all the peripheral PLL counter and clock source */ 700 /* peri_emaca_clk divider */ 701 writel(per_cfg->cntr2clk_cnt | 702 (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), 703 &clock_manager_base->per_pll.cntr2clk); 704 /* peri_emacb_clk divider */ 705 writel(per_cfg->cntr3clk_cnt | 706 (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), 707 &clock_manager_base->per_pll.cntr3clk); 708 /* peri_emac_ptp_clk divider */ 709 writel(per_cfg->cntr4clk_cnt | 710 (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), 711 &clock_manager_base->per_pll.cntr4clk); 712 /* peri_gpio_db_clk divider */ 713 writel(per_cfg->cntr5clk_cnt | 714 (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), 715 &clock_manager_base->per_pll.cntr5clk); 716 /* peri_sdmmc_clk divider */ 717 writel(per_cfg->cntr6clk_cnt | 718 (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), 719 &clock_manager_base->per_pll.cntr6clk); 720 /* peri_s2f_user0_clk divider */ 721 writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); 722 /* peri_s2f_user1_clk divider */ 723 writel(per_cfg->cntr8clk_cnt | 724 (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), 725 &clock_manager_base->per_pll.cntr8clk); 726 /* peri_hmc_pll_clk divider */ 727 writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); 728 729 /* setup all the external PLL counter */ 730 /* mpu wrapper / external divider */ 731 writel(main_cfg->mpuclk_cnt | 732 (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), 733 &clock_manager_base->main_pll.mpuclk); 734 /* NOC wrapper / external divider */ 735 writel(main_cfg->nocclk_cnt | 736 (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), 737 &clock_manager_base->main_pll.nocclk); 738 /* NOC subclock divider such as l4 */ 739 writel(main_cfg->nocdiv_l4mainclk | 740 (main_cfg->nocdiv_l4mpclk << 741 CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | 742 (main_cfg->nocdiv_l4spclk << 743 CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | 744 (main_cfg->nocdiv_csatclk << 745 CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | 746 (main_cfg->nocdiv_cstraceclk << 747 CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | 748 (main_cfg->nocdiv_cspdbclk << 749 CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), 750 &clock_manager_base->main_pll.nocdiv); 751 /* gpio_db external divider */ 752 writel(per_cfg->gpiodiv_gpiodbclk, 753 &clock_manager_base->per_pll.gpiodiv); 754 755 /* setup the EMAC clock mux select */ 756 writel((per_cfg->emacctl_emac0sel << 757 CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | 758 (per_cfg->emacctl_emac1sel << 759 CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | 760 (per_cfg->emacctl_emac2sel << 761 CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), 762 &clock_manager_base->per_pll.emacctl); 763 764 /* at this stage, check for PLL lock status */ 765 cm_wait_for_lock(LOCKED_MASK); 766 767 /* 768 * after locking, but before taking out of bypass, 769 * assert/deassert outresetall 770 */ 771 /* assert mainpll outresetall */ 772 setbits_le32(&clock_manager_base->main_pll.vco0, 773 CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 774 /* assert perpll outresetall */ 775 setbits_le32(&clock_manager_base->per_pll.vco0, 776 CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 777 /* de-assert mainpll outresetall */ 778 clrbits_le32(&clock_manager_base->main_pll.vco0, 779 CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); 780 /* de-assert perpll outresetall */ 781 clrbits_le32(&clock_manager_base->per_pll.vco0, 782 CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); 783 784 /* Take all PLLs out of bypass when boot mode is cleared. */ 785 /* release mainpll from bypass */ 786 writel(CLKMGR_MAINPLL_BYPASS_RESET, 787 &clock_manager_base->main_pll.bypassr); 788 /* wait till Clock Manager is not busy */ 789 cm_wait_for_fsm(); 790 791 /* release perpll from bypass */ 792 writel(CLKMGR_PERPLL_BYPASS_RESET, 793 &clock_manager_base->per_pll.bypassr); 794 /* wait till Clock Manager is not busy */ 795 cm_wait_for_fsm(); 796 797 /* clear boot mode */ 798 clrbits_le32(&clock_manager_base->ctrl, 799 CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); 800 /* wait till Clock Manager is not busy */ 801 cm_wait_for_fsm(); 802 803 /* At here, we need to ramp to final value if needed */ 804 if (pll_ramp_main_hz != 0) 805 cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); 806 if (pll_ramp_periph_hz != 0) 807 cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); 808 809 /* Now ungate non-hw-managed clocks */ 810 writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | 811 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, 812 &clock_manager_base->main_pll.ens); 813 writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); 814 815 /* Clear the loss lock and slip bits as they might set during 816 clock reconfiguration */ 817 writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | 818 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | 819 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | 820 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | 821 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | 822 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, 823 &clock_manager_base->intr); 824 825 return 0; 826 } 827 828 void cm_use_intosc(void) 829 { 830 setbits_le32(&clock_manager_base->ctrl, 831 CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); 832 } 833 834 unsigned int cm_get_noc_clk_hz(void) 835 { 836 unsigned int clk_src, divisor, nocclk, src_hz; 837 838 nocclk = readl(&clock_manager_base->main_pll.nocclk); 839 clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) & 840 CLKMGR_MAINPLL_NOCCLK_SRC_MSK; 841 842 divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK); 843 844 if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) { 845 src_hz = cm_get_main_vco_clk_hz(); 846 src_hz /= 1 + 847 (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) & 848 CLKMGR_MAINPLL_NOCCLK_CNT_MSK); 849 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) { 850 src_hz = cm_get_per_vco_clk_hz(); 851 src_hz /= 1 + 852 ((readl(SOCFPGA_CLKMGR_ADDRESS + 853 CLKMGR_MAINPLL_NOC_CLK_OFFSET) >> 854 CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & 855 CLKMGR_MAINPLL_NOCCLK_CNT_MSK); 856 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) { 857 src_hz = eosc1_hz; 858 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) { 859 src_hz = cb_intosc_hz; 860 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) { 861 src_hz = f2s_free_hz; 862 } else { 863 src_hz = 0; 864 } 865 866 return src_hz / divisor; 867 } 868 869 unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift) 870 { 871 unsigned int divisor2 = 1 << 872 ((readl(&clock_manager_base->main_pll.nocdiv) >> 873 nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK); 874 875 return cm_get_noc_clk_hz() / divisor2; 876 } 877 878 int cm_basic_init(const void *blob) 879 { 880 struct mainpll_cfg main_cfg; 881 struct perpll_cfg per_cfg; 882 struct alteragrp_cfg altrgrp_cfg; 883 int rval; 884 885 /* initialize to zero for use case of optional node */ 886 memset(&main_cfg, 0, sizeof(main_cfg)); 887 memset(&per_cfg, 0, sizeof(per_cfg)); 888 memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg)); 889 890 rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg); 891 if (rval) 892 return rval; 893 894 rval = cm_full_cfg(&main_cfg, &per_cfg); 895 896 cm_l4_main_clk_hz = 897 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); 898 899 cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); 900 901 cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz(); 902 903 cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4; 904 905 return rval; 906 } 907 908 unsigned long cm_get_mpu_clk_hz(void) 909 { 910 u32 reg, clk_hz; 911 u32 clk_src, mainmpuclk_reg; 912 913 mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk); 914 915 clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) & 916 CLKMGR_MAINPLL_MPUCLK_SRC_MSK; 917 918 reg = readl(&clock_manager_base->altera.mpuclk); 919 /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ 920 switch (clk_src) { 921 case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: 922 clk_hz = cm_get_main_vco_clk_hz(); 923 clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 924 break; 925 case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: 926 clk_hz = cm_get_per_vco_clk_hz(); 927 clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & 928 CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); 929 break; 930 case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: 931 clk_hz = eosc1_hz; 932 break; 933 case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: 934 clk_hz = cb_intosc_hz; 935 break; 936 case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: 937 clk_hz = f2s_free_hz; 938 break; 939 default: 940 printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src); 941 return 0; 942 } 943 944 clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; 945 946 return clk_hz; 947 } 948 949 unsigned int cm_get_per_vco_clk_hz(void) 950 { 951 u32 src_hz = 0; 952 u32 clk_src = 0; 953 u32 numer = 0; 954 u32 denom = 0; 955 u32 vco = 0; 956 957 clk_src = readl(&clock_manager_base->per_pll.vco0); 958 959 clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) & 960 CLKMGR_PERPLL_VCO0_PSRC_MSK; 961 962 if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) { 963 src_hz = eosc1_hz; 964 } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) { 965 src_hz = cb_intosc_hz; 966 } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) { 967 src_hz = f2s_free_hz; 968 } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) { 969 src_hz = cm_get_main_vco_clk_hz(); 970 src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) & 971 CLKMGR_MAINPLL_CNTRCLK_MSK) + 1; 972 } else { 973 printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src); 974 return 0; 975 } 976 977 vco = readl(&clock_manager_base->per_pll.vco1); 978 979 numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; 980 981 denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & 982 CLKMGR_PERPLL_VCO1_DENOM_MSK; 983 984 vco = src_hz; 985 vco /= 1 + denom; 986 vco *= 1 + numer; 987 988 return vco; 989 } 990 991 unsigned int cm_get_main_vco_clk_hz(void) 992 { 993 u32 src_hz, numer, denom, vco; 994 995 u32 clk_src = readl(&clock_manager_base->main_pll.vco0); 996 997 clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) & 998 CLKMGR_MAINPLL_VCO0_PSRC_MSK; 999 1000 if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) { 1001 src_hz = eosc1_hz; 1002 } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) { 1003 src_hz = cb_intosc_hz; 1004 } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) { 1005 src_hz = f2s_free_hz; 1006 } else { 1007 printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src); 1008 return 0; 1009 } 1010 1011 vco = readl(&clock_manager_base->main_pll.vco1); 1012 1013 numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK; 1014 1015 denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) & 1016 CLKMGR_MAINPLL_VCO1_DENOM_MSK; 1017 1018 vco = src_hz; 1019 vco /= 1 + denom; 1020 vco *= 1 + numer; 1021 1022 return vco; 1023 } 1024 1025 unsigned int cm_get_l4_sp_clk_hz(void) 1026 { 1027 return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB); 1028 } 1029 1030 unsigned int cm_get_mmc_controller_clk_hz(void) 1031 { 1032 u32 clk_hz = 0; 1033 u32 clk_input = 0; 1034 1035 clk_input = readl(&clock_manager_base->per_pll.cntr6clk); 1036 clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) & 1037 CLKMGR_PERPLLGRP_SRC_MSK; 1038 1039 switch (clk_input) { 1040 case CLKMGR_PERPLLGRP_SRC_MAIN: 1041 clk_hz = cm_get_main_vco_clk_hz(); 1042 clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & 1043 CLKMGR_MAINPLL_CNTRCLK_MSK); 1044 break; 1045 1046 case CLKMGR_PERPLLGRP_SRC_PERI: 1047 clk_hz = cm_get_per_vco_clk_hz(); 1048 clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & 1049 CLKMGR_PERPLL_CNTRCLK_MSK); 1050 break; 1051 1052 case CLKMGR_PERPLLGRP_SRC_OSC1: 1053 clk_hz = eosc1_hz; 1054 break; 1055 1056 case CLKMGR_PERPLLGRP_SRC_INTOSC: 1057 clk_hz = cb_intosc_hz; 1058 break; 1059 1060 case CLKMGR_PERPLLGRP_SRC_FPGA: 1061 clk_hz = f2s_free_hz; 1062 break; 1063 } 1064 1065 return clk_hz / 4; 1066 } 1067 1068 unsigned int cm_get_spi_controller_clk_hz(void) 1069 { 1070 return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); 1071 } 1072 1073 unsigned int cm_get_qspi_controller_clk_hz(void) 1074 { 1075 return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); 1076 } 1077 1078 /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ 1079 int dw_spi_get_clk(struct udevice *bus, ulong *rate) 1080 { 1081 *rate = cm_get_spi_controller_clk_hz(); 1082 1083 return 0; 1084 } 1085 1086 void cm_print_clock_quick_summary(void) 1087 { 1088 printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); 1089 printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); 1090 printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); 1091 printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); 1092 printf("EOSC1 %8d kHz\n", eosc1_hz / 1000); 1093 printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000); 1094 printf("f2s_free %8d kHz\n", f2s_free_hz / 1000); 1095 printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000); 1096 printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000); 1097 printf("L4 Main %8d kHz\n", 1098 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000); 1099 printf("L4 MP %8d kHz\n", 1100 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000); 1101 printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); 1102 printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000); 1103 } 1104