1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <hwconfig.h>
9 #include <netdev.h>
10 #include <linux/compiler.h>
11 #include <asm/mmu.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_fdt.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20 #include "../common/sleep.h"
21 #include "t104xrdb.h"
22 #include "cpld.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
checkboard(void)26 int checkboard(void)
27 {
28 struct cpu_type *cpu = gd->arch.cpu;
29 u8 sw;
30
31 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
32 printf("Board: %sD4RDB\n", cpu->name);
33 #else
34 printf("Board: %sRDB\n", cpu->name);
35 #endif
36 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
37 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
38
39 sw = CPLD_READ(flash_ctl_status);
40 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
41
42 printf("vBank: %d\n", sw);
43
44 return 0;
45 }
46
board_early_init_f(void)47 int board_early_init_f(void)
48 {
49 #if defined(CONFIG_DEEP_SLEEP)
50 if (is_warm_boot())
51 fsl_dp_disable_console();
52 #endif
53
54 return 0;
55 }
56
board_early_init_r(void)57 int board_early_init_r(void)
58 {
59 #ifdef CONFIG_SYS_FLASH_BASE
60 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
61 int flash_esel = find_tlb_idx((void *)flashbase, 1);
62
63 /*
64 * Remap Boot flash region to caching-inhibited
65 * so that flash can be erased properly.
66 */
67
68 /* Flush d-cache and invalidate i-cache of any FLASH data */
69 flush_dcache();
70 invalidate_icache();
71
72 if (flash_esel == -1) {
73 /* very unlikely unless something is messed up */
74 puts("Error: Could not find TLB for FLASH BASE\n");
75 flash_esel = 2; /* give our best effort to continue */
76 } else {
77 /* invalidate existing TLB entry for flash */
78 disable_tlb(flash_esel);
79 }
80
81 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, flash_esel, BOOKE_PAGESZ_256M, 1);
84 #endif
85 return 0;
86 }
87
misc_init_r(void)88 int misc_init_r(void)
89 {
90 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91 u32 srds_s1;
92
93 srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
94
95 printf("SERDES Reference : 0x%X\n", srds_s1);
96
97 /* select SGMII*/
98 if (srds_s1 == 0x86)
99 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
100 MISC_CTL_SG_SEL);
101
102 /* select SGMII and Aurora*/
103 if (srds_s1 == 0x8E)
104 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
105 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
106
107 #if defined(CONFIG_TARGET_T1040D4RDB)
108 if (hwconfig("qe-tdm")) {
109 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
110 MISC_MUX_QE_TDM);
111 printf("QECSR : 0x%02x, mux to qe-tdm\n",
112 CPLD_READ(sfp_ctl_status));
113 }
114 /* Mask all CPLD interrupt sources, except QSGMII interrupts */
115 if (CPLD_READ(sw_ver) < 0x03) {
116 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
117 CPLD_READ(sw_ver));
118 } else {
119 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
120 ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
121 }
122 #endif
123
124 return 0;
125 }
126
ft_board_setup(void * blob,bd_t * bd)127 int ft_board_setup(void *blob, bd_t *bd)
128 {
129 phys_addr_t base;
130 phys_size_t size;
131
132 ft_cpu_setup(blob, bd);
133
134 base = env_get_bootm_low();
135 size = env_get_bootm_size();
136
137 fdt_fixup_memory(blob, (u64)base, (u64)size);
138
139 #ifdef CONFIG_PCI
140 pci_of_setup(blob, bd);
141 #endif
142
143 fdt_fixup_liodn(blob);
144
145 #ifdef CONFIG_HAS_FSL_DR_USB
146 fsl_fdt_fixup_dr_usb(blob, bd);
147 #endif
148
149 #ifdef CONFIG_SYS_DPAA_FMAN
150 fdt_fixup_fman_ethernet(blob);
151 #endif
152
153 if (hwconfig("qe-tdm"))
154 fdt_del_diu(blob);
155 return 0;
156 }
157