1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <ns16550.h>
8 #include <asm/io.h>
9 #include <nand.h>
10 #include <asm/fsl_law.h>
11 #include <fsl_ddr_sdram.h>
12
13
14 const static u32 sysclk_tbl[] = {
15 66666000, 7499900, 83332500, 8999900,
16 99999000, 11111000, 12499800, 13333200
17 };
18
board_init_f(ulong bootflag)19 void board_init_f(ulong bootflag)
20 {
21 int px_spd;
22 u32 plat_ratio, sys_clk, bus_clk;
23 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
24
25 #if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
26 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
27 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
28 #endif
29 /* for FPGA */
30 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
31 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
32
33 /* initialize selected port with appropriate baud rate */
34 px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
35 sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
36 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
37 bus_clk = sys_clk * plat_ratio / 2;
38
39 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
40 bus_clk / 16 / CONFIG_BAUDRATE);
41
42 puts("\nNAND boot... ");
43
44 /* copy code to RAM and jump to it - this should not return */
45 /* NOTE - code has to be copied out of NAND buffer before
46 * other blocks can be read.
47 */
48 relocate_code(CONFIG_SPL_RELOC_STACK, 0,
49 CONFIG_SPL_RELOC_TEXT_BASE);
50 }
51
board_init_r(gd_t * gd,ulong dest_addr)52 void board_init_r(gd_t *gd, ulong dest_addr)
53 {
54 puts("\nSecond program loader running in sram...");
55 nand_boot();
56 }
57
putc(char c)58 void putc(char c)
59 {
60 if (c == '\n')
61 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
62
63 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
64 }
65
puts(const char * str)66 void puts(const char *str)
67 {
68 while (*str)
69 putc(*str++);
70 }
71