1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <display.h> 11 #include <dm.h> 12 #include <edid.h> 13 #include <panel.h> 14 #include <regmap.h> 15 #include <syscon.h> 16 #include <asm/gpio.h> 17 #include <asm/io.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/edp_rk3288.h> 20 #include <asm/arch/grf_rk3288.h> 21 #include <dt-bindings/clock/rk3288-cru.h> 22 23 #define MAX_CR_LOOP 5 24 #define MAX_EQ_LOOP 5 25 #define DP_LINK_STATUS_SIZE 6 26 27 static const char * const voltage_names[] = { 28 "0.4V", "0.6V", "0.8V", "1.2V" 29 }; 30 static const char * const pre_emph_names[] = { 31 "0dB", "3.5dB", "6dB", "9.5dB" 32 }; 33 34 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 35 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 36 37 struct rk_edp_priv { 38 struct rk3288_edp *regs; 39 struct rk3288_grf *grf; 40 struct udevice *panel; 41 struct link_train link_train; 42 u8 train_set[4]; 43 }; 44 45 static void rk_edp_init_refclk(struct rk3288_edp *regs) 46 { 47 writel(SEL_24M, ®s->analog_ctl_2); 48 writel(REF_CLK_24M, ®s->pll_reg_1); 49 50 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US | 51 V2L_CUR_SEL_1MA, ®s->pll_reg_2); 52 53 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET | 54 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE, 55 ®s->pll_reg_3); 56 57 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL | 58 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP, 59 ®s->pll_reg_5); 60 61 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg); 62 63 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 | 64 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL, 65 ®s->tx_common); 66 67 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM, 68 ®s->dp_aux); 69 70 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG, 71 ®s->dp_bias); 72 73 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL, 74 ®s->dp_reserv2); 75 } 76 77 static void rk_edp_init_interrupt(struct rk3288_edp *regs) 78 { 79 /* Set interrupt pin assertion polarity as high */ 80 writel(INT_POL, ®s->int_ctl); 81 82 /* Clear pending registers */ 83 writel(0xff, ®s->common_int_sta_1); 84 writel(0x4f, ®s->common_int_sta_2); 85 writel(0xff, ®s->common_int_sta_3); 86 writel(0x27, ®s->common_int_sta_4); 87 writel(0x7f, ®s->dp_int_sta); 88 89 /* 0:mask,1: unmask */ 90 writel(0x00, ®s->common_int_mask_1); 91 writel(0x00, ®s->common_int_mask_2); 92 writel(0x00, ®s->common_int_mask_3); 93 writel(0x00, ®s->common_int_mask_4); 94 writel(0x00, ®s->int_sta_mask); 95 } 96 97 static void rk_edp_enable_sw_function(struct rk3288_edp *regs) 98 { 99 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N); 100 } 101 102 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs) 103 { 104 u32 val; 105 106 val = readl(®s->dp_debug_ctl); 107 108 return val & PLL_LOCK; 109 } 110 111 static int rk_edp_init_analog_func(struct rk3288_edp *regs) 112 { 113 ulong start; 114 115 writel(0x00, ®s->dp_pd); 116 writel(PLL_LOCK_CHG, ®s->common_int_sta_1); 117 118 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); 119 120 start = get_timer(0); 121 while (!rk_edp_get_pll_locked(regs)) { 122 if (get_timer(start) > PLL_LOCK_TIMEOUT) { 123 printf("%s: PLL is not locked\n", __func__); 124 return -ETIMEDOUT; 125 } 126 } 127 128 /* Enable Serdes FIFO function and Link symbol clock domain module */ 129 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N | 130 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | 131 SSC_FUNC_EN_N); 132 133 return 0; 134 } 135 136 static void rk_edp_init_aux(struct rk3288_edp *regs) 137 { 138 /* Clear inerrupts related to AUX channel */ 139 writel(AUX_FUNC_EN_N, ®s->dp_int_sta); 140 141 /* Disable AUX channel module */ 142 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N); 143 144 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 145 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl); 146 147 /* Enable AUX channel module */ 148 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N); 149 } 150 151 static int rk_edp_aux_enable(struct rk3288_edp *regs) 152 { 153 ulong start; 154 155 setbits_le32(®s->aux_ch_ctl_2, AUX_EN); 156 start = get_timer(0); 157 do { 158 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN)) 159 return 0; 160 } while (get_timer(start) < 20); 161 162 return -ETIMEDOUT; 163 } 164 165 static int rk_edp_is_aux_reply(struct rk3288_edp *regs) 166 { 167 ulong start; 168 169 start = get_timer(0); 170 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) { 171 if (get_timer(start) > 10) 172 return -ETIMEDOUT; 173 } 174 175 writel(RPLY_RECEIV, ®s->dp_int_sta); 176 177 return 0; 178 } 179 180 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs) 181 { 182 int val, ret; 183 184 /* Enable AUX CH operation */ 185 ret = rk_edp_aux_enable(regs); 186 if (ret) { 187 debug("AUX CH enable timeout!\n"); 188 return ret; 189 } 190 191 /* Is AUX CH command reply received? */ 192 if (rk_edp_is_aux_reply(regs)) { 193 debug("AUX CH command reply failed!\n"); 194 return ret; 195 } 196 197 /* Clear interrupt source for AUX CH access error */ 198 val = readl(®s->dp_int_sta); 199 if (val & AUX_ERR) { 200 writel(AUX_ERR, ®s->dp_int_sta); 201 return -EIO; 202 } 203 204 /* Check AUX CH error access status */ 205 val = readl(®s->dp_int_sta); 206 if (val & AUX_STATUS_MASK) { 207 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK); 208 return -EIO; 209 } 210 211 return 0; 212 } 213 214 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs, 215 unsigned int val_addr, u8 *in_data, 216 unsigned int length, 217 enum dpcd_request request) 218 { 219 int val; 220 int i, try_times; 221 u8 *data; 222 int ret = 0; 223 u32 len = 0; 224 225 while (length) { 226 len = min(length, 16U); 227 for (try_times = 0; try_times < 10; try_times++) { 228 data = in_data; 229 /* Clear AUX CH data buffer */ 230 writel(BUF_CLR, ®s->buf_data_ctl); 231 232 /* Select DPCD device address */ 233 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0); 234 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8); 235 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16); 236 237 /* 238 * Set DisplayPort transaction and read 1 byte 239 * If bit 3 is 1, DisplayPort transaction. 240 * If Bit 3 is 0, I2C transaction. 241 */ 242 if (request == DPCD_WRITE) { 243 val = AUX_LENGTH(len) | 244 AUX_TX_COMM_DP_TRANSACTION | 245 AUX_TX_COMM_WRITE; 246 for (i = 0; i < len; i++) 247 writel(*data++, ®s->buf_data[i]); 248 } else 249 val = AUX_LENGTH(len) | 250 AUX_TX_COMM_DP_TRANSACTION | 251 AUX_TX_COMM_READ; 252 253 writel(val, ®s->aux_ch_ctl_1); 254 255 /* Start AUX transaction */ 256 ret = rk_edp_start_aux_transaction(regs); 257 if (ret == 0) 258 break; 259 else 260 printf("read dpcd Aux Transaction fail!\n"); 261 } 262 263 if (ret) 264 return ret; 265 266 if (request == DPCD_READ) { 267 for (i = 0; i < len; i++) 268 *data++ = (u8)readl(®s->buf_data[i]); 269 } 270 271 length -= len; 272 val_addr += len; 273 in_data += len; 274 } 275 276 return 0; 277 } 278 279 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values, 280 size_t size) 281 { 282 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ); 283 } 284 285 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values, 286 size_t size) 287 { 288 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE); 289 } 290 291 292 static int rk_edp_link_power_up(struct rk_edp_priv *edp) 293 { 294 u8 value; 295 int ret; 296 297 /* DP_SET_POWER register is only available on DPCD v1.1 and later */ 298 if (edp->link_train.revision < 0x11) 299 return 0; 300 301 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1); 302 if (ret) 303 return ret; 304 305 value &= ~DP_SET_POWER_MASK; 306 value |= DP_SET_POWER_D0; 307 308 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1); 309 if (ret) 310 return ret; 311 312 /* 313 * According to the DP 1.1 specification, a "Sink Device must exit the 314 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink 315 * Control Field" (register 0x600). 316 */ 317 mdelay(1); 318 319 return 0; 320 } 321 322 static int rk_edp_link_configure(struct rk_edp_priv *edp) 323 { 324 u8 values[2]; 325 326 values[0] = edp->link_train.link_rate; 327 values[1] = edp->link_train.lane_count; 328 329 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values, 330 sizeof(values)); 331 } 332 333 static void rk_edp_set_link_training(struct rk_edp_priv *edp, 334 const u8 *training_values) 335 { 336 int i; 337 338 for (i = 0; i < edp->link_train.lane_count; i++) 339 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]); 340 } 341 342 static u8 edp_link_status(const u8 *link_status, int r) 343 { 344 return link_status[r - DPCD_LANE0_1_STATUS]; 345 } 346 347 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp, 348 u8 *link_status) 349 { 350 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status, 351 DP_LINK_STATUS_SIZE); 352 } 353 354 static u8 edp_get_lane_status(const u8 *link_status, int lane) 355 { 356 int i = DPCD_LANE0_1_STATUS + (lane >> 1); 357 int s = (lane & 1) * 4; 358 u8 l = edp_link_status(link_status, i); 359 360 return (l >> s) & 0xf; 361 } 362 363 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count) 364 { 365 int lane; 366 u8 lane_status; 367 368 for (lane = 0; lane < lane_count; lane++) { 369 lane_status = edp_get_lane_status(link_status, lane); 370 if ((lane_status & DP_LANE_CR_DONE) == 0) 371 return -EIO; 372 } 373 374 return 0; 375 } 376 377 static int rk_edp_channel_eq(const u8 *link_status, int lane_count) 378 { 379 u8 lane_align; 380 u8 lane_status; 381 int lane; 382 383 lane_align = edp_link_status(link_status, 384 DPCD_LANE_ALIGN_STATUS_UPDATED); 385 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 386 return -EIO; 387 for (lane = 0; lane < lane_count; lane++) { 388 lane_status = edp_get_lane_status(link_status, lane); 389 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 390 return -EIO; 391 } 392 393 return 0; 394 } 395 396 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane) 397 { 398 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 399 int s = ((lane & 1) ? 400 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 401 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 402 u8 l = edp_link_status(link_status, i); 403 404 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 405 } 406 407 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status, 408 int lane) 409 { 410 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 411 int s = ((lane & 1) ? 412 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 413 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 414 u8 l = edp_link_status(link_status, i); 415 416 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 417 } 418 419 static void edp_get_adjust_train(const u8 *link_status, int lane_count, 420 u8 train_set[]) 421 { 422 uint v = 0; 423 uint p = 0; 424 int lane; 425 426 for (lane = 0; lane < lane_count; lane++) { 427 uint this_v, this_p; 428 429 this_v = rk_edp_get_adjust_request_voltage(link_status, lane); 430 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status, 431 lane); 432 433 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n", 434 lane, 435 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 436 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 437 438 if (this_v > v) 439 v = this_v; 440 if (this_p > p) 441 p = this_p; 442 } 443 444 if (v >= DP_VOLTAGE_MAX) 445 v |= DP_TRAIN_MAX_SWING_REACHED; 446 447 if (p >= DP_PRE_EMPHASIS_MAX) 448 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 449 450 debug("using signal parameters: voltage %s pre_emph %s\n", 451 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) 452 >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 453 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) 454 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 455 456 for (lane = 0; lane < 4; lane++) 457 train_set[lane] = v | p; 458 } 459 460 static int rk_edp_link_train_cr(struct rk_edp_priv *edp) 461 { 462 struct rk3288_edp *regs = edp->regs; 463 int clock_recovery; 464 uint voltage, tries = 0; 465 u8 status[DP_LINK_STATUS_SIZE]; 466 int i, ret; 467 u8 value; 468 469 value = DP_TRAINING_PATTERN_1; 470 writel(value, ®s->dp_training_ptn_set); 471 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1); 472 if (ret) 473 return ret; 474 memset(edp->train_set, '\0', sizeof(edp->train_set)); 475 476 /* clock recovery loop */ 477 clock_recovery = 0; 478 tries = 0; 479 voltage = 0xff; 480 481 while (1) { 482 rk_edp_set_link_training(edp, edp->train_set); 483 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, 484 edp->train_set, 485 edp->link_train.lane_count); 486 if (ret) 487 return ret; 488 489 mdelay(1); 490 491 ret = rk_edp_dpcd_read_link_status(edp, status); 492 if (ret) { 493 printf("displayport link status failed, ret=%d\n", ret); 494 break; 495 } 496 497 clock_recovery = rk_edp_clock_recovery(status, 498 edp->link_train.lane_count); 499 if (!clock_recovery) 500 break; 501 502 for (i = 0; i < edp->link_train.lane_count; i++) { 503 if ((edp->train_set[i] & 504 DP_TRAIN_MAX_SWING_REACHED) == 0) 505 break; 506 } 507 if (i == edp->link_train.lane_count) { 508 printf("clock recovery reached max voltage\n"); 509 break; 510 } 511 512 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 513 voltage) { 514 if (++tries == MAX_CR_LOOP) { 515 printf("clock recovery tried 5 times\n"); 516 break; 517 } 518 } else { 519 tries = 0; 520 } 521 522 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 523 524 /* Compute new train_set as requested by sink */ 525 edp_get_adjust_train(status, edp->link_train.lane_count, 526 edp->train_set); 527 } 528 if (clock_recovery) { 529 printf("clock recovery failed: %d\n", clock_recovery); 530 return clock_recovery; 531 } else { 532 debug("clock recovery at voltage %d pre-emphasis %d\n", 533 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 534 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 535 DP_TRAIN_PRE_EMPHASIS_SHIFT); 536 return 0; 537 } 538 } 539 540 static int rk_edp_link_train_ce(struct rk_edp_priv *edp) 541 { 542 struct rk3288_edp *regs = edp->regs; 543 int channel_eq; 544 u8 value; 545 int tries; 546 u8 status[DP_LINK_STATUS_SIZE]; 547 int ret; 548 549 value = DP_TRAINING_PATTERN_2; 550 writel(value, ®s->dp_training_ptn_set); 551 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1); 552 if (ret) 553 return ret; 554 555 /* channel equalization loop */ 556 channel_eq = 0; 557 for (tries = 0; tries < 5; tries++) { 558 rk_edp_set_link_training(edp, edp->train_set); 559 udelay(400); 560 561 if (rk_edp_dpcd_read_link_status(edp, status) < 0) { 562 printf("displayport link status failed\n"); 563 return -1; 564 } 565 566 channel_eq = rk_edp_channel_eq(status, 567 edp->link_train.lane_count); 568 if (!channel_eq) 569 break; 570 edp_get_adjust_train(status, edp->link_train.lane_count, 571 edp->train_set); 572 } 573 574 if (channel_eq) { 575 printf("channel eq failed, ret=%d\n", channel_eq); 576 return channel_eq; 577 } 578 579 debug("channel eq at voltage %d pre-emphasis %d\n", 580 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 581 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 582 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 583 584 return 0; 585 } 586 587 static int rk_edp_init_training(struct rk_edp_priv *edp) 588 { 589 u8 values[3]; 590 int ret; 591 592 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values, 593 sizeof(values)); 594 if (ret < 0) 595 return ret; 596 597 edp->link_train.revision = values[0]; 598 edp->link_train.link_rate = values[1]; 599 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK; 600 601 debug("max link rate:%d.%dGps max number of lanes:%d\n", 602 edp->link_train.link_rate * 27 / 100, 603 edp->link_train.link_rate * 27 % 100, 604 edp->link_train.lane_count); 605 606 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) && 607 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) { 608 debug("Rx Max Link Rate is abnormal :%x\n", 609 edp->link_train.link_rate); 610 return -EPERM; 611 } 612 613 if (edp->link_train.lane_count == 0) { 614 debug("Rx Max Lane count is abnormal :%x\n", 615 edp->link_train.lane_count); 616 return -EPERM; 617 } 618 619 ret = rk_edp_link_power_up(edp); 620 if (ret) 621 return ret; 622 623 return rk_edp_link_configure(edp); 624 } 625 626 static int rk_edp_hw_link_training(struct rk_edp_priv *edp) 627 { 628 ulong start; 629 u32 val; 630 int ret; 631 632 /* Set link rate and count as you want to establish */ 633 writel(edp->link_train.link_rate, &edp->regs->link_bw_set); 634 writel(edp->link_train.lane_count, &edp->regs->lane_count_set); 635 636 ret = rk_edp_link_train_cr(edp); 637 if (ret) 638 return ret; 639 ret = rk_edp_link_train_ce(edp); 640 if (ret) 641 return ret; 642 643 writel(HW_LT_EN, &edp->regs->dp_hw_link_training); 644 start = get_timer(0); 645 do { 646 val = readl(&edp->regs->dp_hw_link_training); 647 if (!(val & HW_LT_EN)) 648 break; 649 } while (get_timer(start) < 10); 650 651 if (val & HW_LT_ERR_CODE_MASK) { 652 printf("edp hw link training error: %d\n", 653 val >> HW_LT_ERR_CODE_SHIFT); 654 return -EIO; 655 } 656 657 return 0; 658 } 659 660 static int rk_edp_select_i2c_device(struct rk3288_edp *regs, 661 unsigned int device_addr, 662 unsigned int val_addr) 663 { 664 int ret; 665 666 /* Set EDID device address */ 667 writel(device_addr, ®s->aux_addr_7_0); 668 writel(0x0, ®s->aux_addr_15_8); 669 writel(0x0, ®s->aux_addr_19_16); 670 671 /* Set offset from base address of EDID device */ 672 writel(val_addr, ®s->buf_data[0]); 673 674 /* 675 * Set I2C transaction and write address 676 * If bit 3 is 1, DisplayPort transaction. 677 * If Bit 3 is 0, I2C transaction. 678 */ 679 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 680 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1); 681 682 /* Start AUX transaction */ 683 ret = rk_edp_start_aux_transaction(regs); 684 if (ret != 0) { 685 debug("select_i2c_device Aux Transaction fail!\n"); 686 return ret; 687 } 688 689 return 0; 690 } 691 692 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr, 693 unsigned int val_addr, unsigned int count, u8 edid[]) 694 { 695 u32 val; 696 unsigned int i, j; 697 unsigned int cur_data_idx; 698 unsigned int defer = 0; 699 int ret = 0; 700 701 for (i = 0; i < count; i += 16) { 702 for (j = 0; j < 10; j++) { /* try 10 times */ 703 /* Clear AUX CH data buffer */ 704 writel(BUF_CLR, ®s->buf_data_ctl); 705 706 /* Set normal AUX CH command */ 707 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY); 708 709 /* 710 * If Rx sends defer, Tx sends only reads 711 * request without sending addres 712 */ 713 if (!defer) { 714 ret = rk_edp_select_i2c_device(regs, 715 device_addr, 716 val_addr + i); 717 } else { 718 defer = 0; 719 } 720 721 /* 722 * Set I2C transaction and write data 723 * If bit 3 is 1, DisplayPort transaction. 724 * If Bit 3 is 0, I2C transaction. 725 */ 726 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION | 727 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1); 728 729 /* Start AUX transaction */ 730 ret = rk_edp_start_aux_transaction(regs); 731 if (ret == 0) { 732 break; 733 } else { 734 debug("Aux Transaction fail!\n"); 735 continue; 736 } 737 738 /* Check if Rx sends defer */ 739 val = readl(®s->aux_rx_comm); 740 if (val == AUX_RX_COMM_AUX_DEFER || 741 val == AUX_RX_COMM_I2C_DEFER) { 742 debug("Defer: %d\n\n", val); 743 defer = 1; 744 } 745 } 746 747 if (ret) 748 return ret; 749 750 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 751 val = readl(®s->buf_data[cur_data_idx]); 752 edid[i + cur_data_idx] = (u8)val; 753 } 754 } 755 756 return 0; 757 } 758 759 static int rk_edp_set_link_train(struct rk_edp_priv *edp) 760 { 761 int ret; 762 763 ret = rk_edp_init_training(edp); 764 if (ret) { 765 printf("DP LT init failed!\n"); 766 return ret; 767 } 768 769 ret = rk_edp_hw_link_training(edp); 770 if (ret) 771 return ret; 772 773 return 0; 774 } 775 776 static void rk_edp_init_video(struct rk3288_edp *regs) 777 { 778 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG, 779 ®s->common_int_sta_1); 780 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2); 781 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8); 782 } 783 784 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs) 785 { 786 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); 787 } 788 789 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs, 790 enum clock_recovery_m_value_type type, 791 u32 m_value, 792 u32 n_value) 793 { 794 if (type == REGISTER_M) { 795 setbits_le32(®s->sys_ctl_4, FIX_M_VID); 796 writel(m_value & 0xff, ®s->m_vid_0); 797 writel((m_value >> 8) & 0xff, ®s->m_vid_1); 798 writel((m_value >> 16) & 0xff, ®s->m_vid_2); 799 800 writel(n_value & 0xf, ®s->n_vid_0); 801 writel((n_value >> 8) & 0xff, ®s->n_vid_1); 802 writel((n_value >> 16) & 0xff, ®s->n_vid_2); 803 } else { 804 clrbits_le32(®s->sys_ctl_4, FIX_M_VID); 805 806 writel(0x00, ®s->n_vid_0); 807 writel(0x80, ®s->n_vid_1); 808 writel(0x00, ®s->n_vid_2); 809 } 810 } 811 812 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs) 813 { 814 ulong start; 815 u32 val; 816 817 start = get_timer(0); 818 do { 819 val = readl(®s->sys_ctl_1); 820 821 /* must write value to update DET_STA bit status */ 822 writel(val, ®s->sys_ctl_1); 823 val = readl(®s->sys_ctl_1); 824 if (!(val & DET_STA)) 825 continue; 826 827 val = readl(®s->sys_ctl_2); 828 829 /* must write value to update CHA_STA bit status */ 830 writel(val, ®s->sys_ctl_2); 831 val = readl(®s->sys_ctl_2); 832 if (!(val & CHA_STA)) 833 return 0; 834 835 } while (get_timer(start) < 100); 836 837 return -ETIMEDOUT; 838 } 839 840 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp) 841 { 842 ulong start; 843 u32 val; 844 845 start = get_timer(0); 846 do { 847 val = readl(&edp->regs->sys_ctl_3); 848 849 /* must write value to update STRM_VALID bit status */ 850 writel(val, &edp->regs->sys_ctl_3); 851 852 val = readl(&edp->regs->sys_ctl_3); 853 if (!(val & STRM_VALID)) 854 return 0; 855 } while (get_timer(start) < 100); 856 857 return -ETIMEDOUT; 858 } 859 860 static int rk_edp_config_video(struct rk_edp_priv *edp) 861 { 862 int ret; 863 864 rk_edp_config_video_slave_mode(edp->regs); 865 866 if (!rk_edp_get_pll_locked(edp->regs)) { 867 debug("PLL is not locked yet.\n"); 868 return -ETIMEDOUT; 869 } 870 871 ret = rk_edp_is_video_stream_clock_on(edp->regs); 872 if (ret) 873 return ret; 874 875 /* Set to use the register calculated M/N video */ 876 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0); 877 878 /* For video bist, Video timing must be generated by register */ 879 clrbits_le32(&edp->regs->video_ctl_10, F_SEL); 880 881 /* Disable video mute */ 882 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); 883 884 /* Enable video at next frame */ 885 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN); 886 887 return rk_edp_is_video_stream_on(edp); 888 } 889 890 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp) 891 { 892 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL); 893 } 894 895 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp) 896 { 897 u32 val; 898 899 val = readl(&edp->regs->sys_ctl_3); 900 if (val & HPD_STATUS) 901 return 1; 902 903 return 0; 904 } 905 906 /* 907 * support edp HPD function 908 * some hardware version do not support edp hdp, 909 * we use 200ms to try to get the hpd single now, 910 * if we can not get edp hpd single, it will delay 200ms, 911 * also meet the edp power timing request, to compatible 912 * all of the hardware version 913 */ 914 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp) 915 { 916 ulong start; 917 918 start = get_timer(0); 919 do { 920 if (rockchip_edp_get_plug_in_status(edp)) 921 return; 922 udelay(100); 923 } while (get_timer(start) < 200); 924 925 debug("do not get hpd single, force hpd\n"); 926 rockchip_edp_force_hpd(edp); 927 } 928 929 static int rk_edp_enable(struct udevice *dev, int panel_bpp, 930 const struct display_timing *edid) 931 { 932 struct rk_edp_priv *priv = dev_get_priv(dev); 933 int ret = 0; 934 935 ret = rk_edp_set_link_train(priv); 936 if (ret) { 937 printf("link train failed!\n"); 938 return ret; 939 } 940 941 rk_edp_init_video(priv->regs); 942 ret = rk_edp_config_video(priv); 943 if (ret) { 944 printf("config video failed\n"); 945 return ret; 946 } 947 ret = panel_enable_backlight(priv->panel); 948 if (ret) { 949 debug("%s: backlight error: %d\n", __func__, ret); 950 return ret; 951 } 952 953 return 0; 954 } 955 956 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size) 957 { 958 struct rk_edp_priv *priv = dev_get_priv(dev); 959 u32 edid_size = EDID_LENGTH; 960 int ret; 961 int i; 962 963 for (i = 0; i < 3; i++) { 964 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER, 965 EDID_LENGTH, &buf[EDID_HEADER]); 966 if (ret) { 967 debug("EDID read failed\n"); 968 continue; 969 } 970 971 /* 972 * check if the EDID has an extension flag, and read additional 973 * EDID data if needed 974 */ 975 if (buf[EDID_EXTENSION_FLAG]) { 976 edid_size += EDID_LENGTH; 977 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, 978 EDID_LENGTH, EDID_LENGTH, 979 &buf[EDID_LENGTH]); 980 if (ret) { 981 debug("EDID Read failed!\n"); 982 continue; 983 } 984 } 985 goto done; 986 } 987 988 /* After 3 attempts, give up */ 989 return ret; 990 991 done: 992 return edid_size; 993 } 994 995 static int rk_edp_ofdata_to_platdata(struct udevice *dev) 996 { 997 struct rk_edp_priv *priv = dev_get_priv(dev); 998 999 priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev); 1000 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1001 1002 return 0; 1003 } 1004 1005 static int rk_edp_remove(struct udevice *dev) 1006 { 1007 struct rk_edp_priv *priv = dev_get_priv(dev); 1008 struct rk3288_edp *regs = priv->regs; 1009 1010 setbits_le32(®s->video_ctl_1, VIDEO_MUTE); 1011 clrbits_le32(®s->video_ctl_1, VIDEO_EN); 1012 clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL); 1013 setbits_le32(®s->func_en_1, SW_FUNC_EN_N); 1014 1015 return 0; 1016 } 1017 1018 static int rk_edp_probe(struct udevice *dev) 1019 { 1020 struct display_plat *uc_plat = dev_get_uclass_platdata(dev); 1021 struct rk_edp_priv *priv = dev_get_priv(dev); 1022 struct rk3288_edp *regs = priv->regs; 1023 struct clk clk; 1024 int ret; 1025 1026 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel", 1027 &priv->panel); 1028 if (ret) { 1029 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, 1030 dev->name, ret); 1031 return ret; 1032 } 1033 1034 int vop_id = uc_plat->source_id; 1035 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id); 1036 1037 ret = clk_get_by_index(dev, 1, &clk); 1038 if (ret >= 0) { 1039 ret = clk_set_rate(&clk, 0); 1040 clk_free(&clk); 1041 } 1042 if (ret) { 1043 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); 1044 return ret; 1045 } 1046 1047 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); 1048 if (ret >= 0) { 1049 ret = clk_set_rate(&clk, 192000000); 1050 clk_free(&clk); 1051 } 1052 if (ret < 0) { 1053 debug("%s: Failed to set clock in source device '%s': ret=%d\n", 1054 __func__, uc_plat->src_dev->name, ret); 1055 return ret; 1056 } 1057 1058 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */ 1059 rk_setreg(&priv->grf->soc_con12, 1 << 4); 1060 1061 /* select epd signal from vop0 or vop1 */ 1062 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5)); 1063 1064 rockchip_edp_wait_hpd(priv); 1065 1066 rk_edp_init_refclk(regs); 1067 rk_edp_init_interrupt(regs); 1068 rk_edp_enable_sw_function(regs); 1069 ret = rk_edp_init_analog_func(regs); 1070 if (ret) 1071 return ret; 1072 rk_edp_init_aux(regs); 1073 1074 return 0; 1075 } 1076 1077 static const struct dm_display_ops dp_rockchip_ops = { 1078 .read_edid = rk_edp_read_edid, 1079 .enable = rk_edp_enable, 1080 }; 1081 1082 static const struct udevice_id rockchip_dp_ids[] = { 1083 { .compatible = "rockchip,rk3288-edp" }, 1084 { } 1085 }; 1086 1087 U_BOOT_DRIVER(dp_rockchip) = { 1088 .name = "edp_rockchip", 1089 .id = UCLASS_DISPLAY, 1090 .of_match = rockchip_dp_ids, 1091 .ops = &dp_rockchip_ops, 1092 .ofdata_to_platdata = rk_edp_ofdata_to_platdata, 1093 .probe = rk_edp_probe, 1094 .remove = rk_edp_remove, 1095 .priv_auto_alloc_size = sizeof(struct rk_edp_priv), 1096 }; 1097