1 /* 2 * Copyright 2015 Xilinx, Inc. 3 * 4 * Zynq USB HOST xHCI Controller 5 * 6 * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> 7 * 8 * This file was reused from Freescale USB xHCI 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <usb.h> 15 #include <linux/errno.h> 16 #include <asm/arch-zynqmp/hardware.h> 17 #include <linux/compat.h> 18 #include <linux/usb/dwc3.h> 19 #include "xhci.h" 20 21 /* Declare global data pointer */ 22 /* Default to the ZYNQMP XHCI defines */ 23 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 24 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 25 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 26 #define USB3_PHY_RX_POWERON BIT(14) 27 #define USB3_PHY_TX_POWERON BIT(15) 28 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 29 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 30 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 31 32 /* USBOTGSS_WRAPPER definitions */ 33 #define USBOTGSS_WRAPRESET BIT(17) 34 #define USBOTGSS_DMADISABLE BIT(16) 35 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 36 #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 37 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 38 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 39 #define USBOTGSS_IDLEMODE_SMRT BIT(3) 40 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 41 42 /* USBOTGSS_IRQENABLE_SET_0 bit */ 43 #define USBOTGSS_COREIRQ_EN BIT(1) 44 45 /* USBOTGSS_IRQENABLE_SET_1 bits */ 46 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 47 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 48 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 49 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 50 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 51 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 52 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 53 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 54 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 55 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 56 57 struct zynqmp_xhci { 58 struct xhci_hccr *hcd; 59 struct dwc3 *dwc3_reg; 60 }; 61 62 static struct zynqmp_xhci zynqmp_xhci; 63 64 unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; 65 66 static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) 67 { 68 int ret = 0; 69 70 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); 71 if (ret) { 72 debug("%s:failed to initialize core\n", __func__); 73 return ret; 74 } 75 76 /* We are hard-coding DWC3 core to Host Mode */ 77 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 78 79 return ret; 80 } 81 82 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 83 { 84 struct zynqmp_xhci *ctx = &zynqmp_xhci; 85 int ret = 0; 86 uint32_t hclen; 87 88 if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) 89 return -EINVAL; 90 91 ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; 92 ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET); 93 94 ret = board_usb_init(index, USB_INIT_HOST); 95 if (ret != 0) { 96 puts("Failed to initialize board for USB\n"); 97 return ret; 98 } 99 100 ret = zynqmp_xhci_core_init(ctx); 101 if (ret < 0) { 102 puts("Failed to initialize xhci\n"); 103 return ret; 104 } 105 106 *hccr = (struct xhci_hccr *)ctx->hcd; 107 hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)); 108 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen); 109 110 debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n", 111 *hccr, *hcor, hclen); 112 113 return ret; 114 } 115 116 void xhci_hcd_stop(int index) 117 { 118 /* 119 * Currently zynqmp socs do not support PHY shutdown from 120 * sw. But this support may be added in future socs. 121 */ 122 123 return; 124 } 125