1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * All rights reserved. 4 * 5 * This file contains only support functions used also by the SoCFPGA 6 * platform code, the real meat is located in drivers/fpga/socfpga.c . 7 * 8 * SPDX-License-Identifier: BSD-3-Clause 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <linux/errno.h> 14 #include <asm/arch/fpga_manager.h> 15 #include <asm/arch/reset_manager.h> 16 #include <asm/arch/system_manager.h> 17 18 /* Timeout count */ 19 #define FPGA_TIMEOUT_CNT 0x1000000 20 21 static struct socfpga_fpga_manager *fpgamgr_regs = 22 (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; 23 24 /* Check whether FPGA Init_Done signal is high */ 25 static int is_fpgamgr_initdone_high(void) 26 { 27 unsigned long val; 28 29 val = readl(&fpgamgr_regs->gpio_ext_porta); 30 return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; 31 } 32 33 /* Get the FPGA mode */ 34 int fpgamgr_get_mode(void) 35 { 36 unsigned long val; 37 38 val = readl(&fpgamgr_regs->stat); 39 return val & FPGAMGRREGS_STAT_MODE_MASK; 40 } 41 42 /* Check whether FPGA is ready to be accessed */ 43 int fpgamgr_test_fpga_ready(void) 44 { 45 /* Check for init done signal */ 46 if (!is_fpgamgr_initdone_high()) 47 return 0; 48 49 /* Check again to avoid false glitches */ 50 if (!is_fpgamgr_initdone_high()) 51 return 0; 52 53 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) 54 return 0; 55 56 return 1; 57 } 58 59 /* Poll until FPGA is ready to be accessed or timeout occurred */ 60 int fpgamgr_poll_fpga_ready(void) 61 { 62 unsigned long i; 63 64 /* If FPGA is blank, wait till WD invoke warm reset */ 65 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { 66 /* check for init done signal */ 67 if (!is_fpgamgr_initdone_high()) 68 continue; 69 /* check again to avoid false glitches */ 70 if (!is_fpgamgr_initdone_high()) 71 continue; 72 return 1; 73 } 74 75 return 0; 76 } 77