1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/addrspace.h> 10 #include <asm/types.h> 11 #include <mach/ar71xx_regs.h> 12 #include <mach/ddr.h> 13 #include <mach/ath79.h> 14 #include <debug_uart.h> 15 16 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 17 void board_debug_uart_init(void) 18 { 19 void __iomem *regs; 20 u32 val; 21 22 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, 23 MAP_NOCACHE); 24 25 /* 26 * GPIO9 as input, GPIO10 as output 27 */ 28 val = readl(regs + AR71XX_GPIO_REG_OE); 29 val |= QCA953X_GPIO(9); 30 val &= ~QCA953X_GPIO(10); 31 writel(val, regs + AR71XX_GPIO_REG_OE); 32 33 /* 34 * Enable GPIO10 as UART0_SOUT 35 */ 36 val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); 37 val &= ~QCA953X_GPIO_MUX_MASK(16); 38 val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; 39 writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); 40 41 /* 42 * Enable GPIO9 as UART0_SIN 43 */ 44 val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); 45 val &= ~QCA953X_GPIO_MUX_MASK(8); 46 val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; 47 writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); 48 49 /* 50 * Enable GPIO10 output 51 */ 52 val = readl(regs + AR71XX_GPIO_REG_OUT); 53 val |= QCA953X_GPIO(10); 54 writel(val, regs + AR71XX_GPIO_REG_OUT); 55 } 56 #endif 57 58 int board_early_init_f(void) 59 { 60 ddr_init(); 61 ath79_eth_reset(); 62 return 0; 63 } 64