1 /* 2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Engicam S.r.l. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <spl.h> 11 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <linux/sizes.h> 15 16 #include <asm/arch/clock.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/iomux.h> 19 #include <asm/arch/mx6-ddr.h> 20 #include <asm/arch/mx6-pins.h> 21 #include <asm/arch/sys_proto.h> 22 23 #include <asm/mach-imx/iomux-v3.h> 24 #include <asm/mach-imx/video.h> 25 26 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 static iomux_v3_cfg_t const uart_pads[] = { 31 #ifdef CONFIG_MX6QDL 32 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 33 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 34 #elif CONFIG_MX6UL 35 IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), 36 IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), 37 #endif 38 }; 39 40 #ifdef CONFIG_SPL_LOAD_FIT 41 int board_fit_config_name_match(const char *name) 42 { 43 if (is_mx6dq() && !strcmp(name, "imx6q-icore")) 44 return 0; 45 else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) 46 return 0; 47 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) 48 return 0; 49 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) 50 return 0; 51 else 52 return -1; 53 } 54 #endif 55 56 #ifdef CONFIG_ENV_IS_IN_MMC 57 void board_boot_order(u32 *spl_boot_list) 58 { 59 u32 bmode = imx6_src_get_boot_mode(); 60 u8 boot_dev = BOOT_DEVICE_MMC1; 61 62 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { 63 case IMX6_BMODE_SD: 64 case IMX6_BMODE_ESD: 65 /* SD/eSD - BOOT_DEVICE_MMC1 */ 66 break; 67 case IMX6_BMODE_MMC: 68 case IMX6_BMODE_EMMC: 69 /* MMC/eMMC */ 70 boot_dev = BOOT_DEVICE_MMC2; 71 break; 72 default: 73 /* Default - BOOT_DEVICE_MMC1 */ 74 printf("Wrong board boot order\n"); 75 break; 76 } 77 78 spl_boot_list[0] = boot_dev; 79 } 80 #endif 81 82 #ifdef CONFIG_SPL_OS_BOOT 83 int spl_start_uboot(void) 84 { 85 /* break into full u-boot on 'c' */ 86 if (serial_tstc() && serial_getc() == 'c') 87 return 1; 88 89 return 0; 90 } 91 #endif 92 93 #ifdef CONFIG_MX6QDL 94 /* 95 * Driving strength: 96 * 0x30 == 40 Ohm 97 * 0x28 == 48 Ohm 98 */ 99 #define IMX6DQ_DRIVE_STRENGTH 0x30 100 #define IMX6SDL_DRIVE_STRENGTH 0x28 101 102 /* configure MX6Q/DUAL mmdc DDR io registers */ 103 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 104 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 105 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 106 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 107 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 108 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 109 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 110 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 111 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 112 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 113 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 114 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 115 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 116 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 117 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 118 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 119 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 120 .dram_cas = IMX6DQ_DRIVE_STRENGTH, 121 .dram_ras = IMX6DQ_DRIVE_STRENGTH, 122 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 123 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 124 .dram_reset = IMX6DQ_DRIVE_STRENGTH, 125 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 126 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 127 .dram_sdba2 = 0x00000000, 128 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 129 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 130 }; 131 132 /* configure MX6Q/DUAL mmdc GRP io registers */ 133 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 134 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 135 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 136 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 137 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 138 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 139 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 140 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 141 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 142 .grp_addds = IMX6DQ_DRIVE_STRENGTH, 143 .grp_ddrmode_ctl = 0x00020000, 144 .grp_ddrpke = 0x00000000, 145 .grp_ddrmode = 0x00020000, 146 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 147 .grp_ddr_type = 0x000c0000, 148 }; 149 150 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 151 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 152 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 153 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 154 .dram_cas = IMX6SDL_DRIVE_STRENGTH, 155 .dram_ras = IMX6SDL_DRIVE_STRENGTH, 156 .dram_reset = IMX6SDL_DRIVE_STRENGTH, 157 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 158 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 159 .dram_sdba2 = 0x00000000, 160 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 161 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 162 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 163 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 164 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 165 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 166 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 167 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 168 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 169 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 170 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 171 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 172 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 173 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 174 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 175 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 176 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 177 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 178 }; 179 180 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 181 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 182 .grp_ddr_type = 0x000c0000, 183 .grp_ddrmode_ctl = 0x00020000, 184 .grp_ddrpke = 0x00000000, 185 .grp_addds = IMX6SDL_DRIVE_STRENGTH, 186 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 187 .grp_ddrmode = 0x00020000, 188 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 189 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 190 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 191 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 192 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 193 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 194 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 195 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 196 }; 197 198 /* mt41j256 */ 199 static struct mx6_ddr3_cfg mt41j256 = { 200 .mem_speed = 1066, 201 .density = 2, 202 .width = 16, 203 .banks = 8, 204 .rowaddr = 13, 205 .coladdr = 10, 206 .pagesz = 2, 207 .trcd = 1375, 208 .trcmin = 4875, 209 .trasmin = 3500, 210 .SRT = 0, 211 }; 212 213 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 214 .p0_mpwldectrl0 = 0x000E0009, 215 .p0_mpwldectrl1 = 0x0018000E, 216 .p1_mpwldectrl0 = 0x00000007, 217 .p1_mpwldectrl1 = 0x00000000, 218 .p0_mpdgctrl0 = 0x43280334, 219 .p0_mpdgctrl1 = 0x031C0314, 220 .p1_mpdgctrl0 = 0x4318031C, 221 .p1_mpdgctrl1 = 0x030C0258, 222 .p0_mprddlctl = 0x3E343A40, 223 .p1_mprddlctl = 0x383C3844, 224 .p0_mpwrdlctl = 0x40404440, 225 .p1_mpwrdlctl = 0x4C3E4446, 226 }; 227 228 /* DDR 64bit */ 229 static struct mx6_ddr_sysinfo mem_q = { 230 .ddr_type = DDR_TYPE_DDR3, 231 .dsize = 2, 232 .cs1_mirror = 0, 233 /* config for full 4GB range so that get_mem_size() works */ 234 .cs_density = 32, 235 .ncs = 1, 236 .bi_on = 1, 237 .rtt_nom = 2, 238 .rtt_wr = 2, 239 .ralat = 5, 240 .walat = 0, 241 .mif3_mode = 3, 242 .rst_to_cke = 0x23, 243 .sde_to_rst = 0x10, 244 }; 245 246 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 247 .p0_mpwldectrl0 = 0x001F0024, 248 .p0_mpwldectrl1 = 0x00110018, 249 .p1_mpwldectrl0 = 0x001F0024, 250 .p1_mpwldectrl1 = 0x00110018, 251 .p0_mpdgctrl0 = 0x4230022C, 252 .p0_mpdgctrl1 = 0x02180220, 253 .p1_mpdgctrl0 = 0x42440248, 254 .p1_mpdgctrl1 = 0x02300238, 255 .p0_mprddlctl = 0x44444A48, 256 .p1_mprddlctl = 0x46484A42, 257 .p0_mpwrdlctl = 0x38383234, 258 .p1_mpwrdlctl = 0x3C34362E, 259 }; 260 261 /* DDR 64bit 1GB */ 262 static struct mx6_ddr_sysinfo mem_dl = { 263 .dsize = 2, 264 .cs1_mirror = 0, 265 /* config for full 4GB range so that get_mem_size() works */ 266 .cs_density = 32, 267 .ncs = 1, 268 .bi_on = 1, 269 .rtt_nom = 1, 270 .rtt_wr = 1, 271 .ralat = 5, 272 .walat = 0, 273 .mif3_mode = 3, 274 .rst_to_cke = 0x23, 275 .sde_to_rst = 0x10, 276 }; 277 278 /* DDR 32bit 512MB */ 279 static struct mx6_ddr_sysinfo mem_s = { 280 .dsize = 1, 281 .cs1_mirror = 0, 282 /* config for full 4GB range so that get_mem_size() works */ 283 .cs_density = 32, 284 .ncs = 1, 285 .bi_on = 1, 286 .rtt_nom = 1, 287 .rtt_wr = 1, 288 .ralat = 5, 289 .walat = 0, 290 .mif3_mode = 3, 291 .rst_to_cke = 0x23, 292 .sde_to_rst = 0x10, 293 }; 294 #endif /* CONFIG_MX6QDL */ 295 296 #ifdef CONFIG_MX6UL 297 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 298 .grp_addds = 0x00000030, 299 .grp_ddrmode_ctl = 0x00020000, 300 .grp_b0ds = 0x00000030, 301 .grp_ctlds = 0x00000030, 302 .grp_b1ds = 0x00000030, 303 .grp_ddrpke = 0x00000000, 304 .grp_ddrmode = 0x00020000, 305 .grp_ddr_type = 0x000c0000, 306 }; 307 308 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 309 .dram_dqm0 = 0x00000030, 310 .dram_dqm1 = 0x00000030, 311 .dram_ras = 0x00000030, 312 .dram_cas = 0x00000030, 313 .dram_odt0 = 0x00000030, 314 .dram_odt1 = 0x00000030, 315 .dram_sdba2 = 0x00000000, 316 .dram_sdclk_0 = 0x00000008, 317 .dram_sdqs0 = 0x00000038, 318 .dram_sdqs1 = 0x00000030, 319 .dram_reset = 0x00000030, 320 }; 321 322 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 323 .p0_mpwldectrl0 = 0x00070007, 324 .p0_mpdgctrl0 = 0x41490145, 325 .p0_mprddlctl = 0x40404546, 326 .p0_mpwrdlctl = 0x4040524D, 327 }; 328 329 struct mx6_ddr_sysinfo ddr_sysinfo = { 330 .dsize = 0, 331 .cs_density = 20, 332 .ncs = 1, 333 .cs1_mirror = 0, 334 .rtt_wr = 2, 335 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 336 .walat = 1, /* Write additional latency */ 337 .ralat = 5, /* Read additional latency */ 338 .mif3_mode = 3, /* Command prediction working mode */ 339 .bi_on = 1, /* Bank interleaving enabled */ 340 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 341 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 342 .ddr_type = DDR_TYPE_DDR3, 343 }; 344 345 static struct mx6_ddr3_cfg mem_ddr = { 346 .mem_speed = 800, 347 .density = 4, 348 .width = 16, 349 .banks = 8, 350 #ifdef TARGET_MX6UL_ISIOT 351 .rowaddr = 15, 352 #else 353 .rowaddr = 13, 354 #endif 355 .coladdr = 10, 356 .pagesz = 2, 357 .trcd = 1375, 358 .trcmin = 4875, 359 .trasmin = 3500, 360 }; 361 #endif /* CONFIG_MX6UL */ 362 363 static void ccgr_init(void) 364 { 365 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 366 367 #ifdef CONFIG_MX6QDL 368 writel(0x00003F3F, &ccm->CCGR0); 369 writel(0x0030FC00, &ccm->CCGR1); 370 writel(0x000FC000, &ccm->CCGR2); 371 writel(0x3F300000, &ccm->CCGR3); 372 writel(0xFF00F300, &ccm->CCGR4); 373 writel(0x0F0000C3, &ccm->CCGR5); 374 writel(0x000003CC, &ccm->CCGR6); 375 #elif CONFIG_MX6UL 376 writel(0x00c03f3f, &ccm->CCGR0); 377 writel(0xfcffff00, &ccm->CCGR1); 378 writel(0x0cffffcc, &ccm->CCGR2); 379 writel(0x3f3c3030, &ccm->CCGR3); 380 writel(0xff00fffc, &ccm->CCGR4); 381 writel(0x033f30ff, &ccm->CCGR5); 382 writel(0x00c00fff, &ccm->CCGR6); 383 #endif 384 } 385 386 static void spl_dram_init(void) 387 { 388 #ifdef CONFIG_MX6QDL 389 if (is_mx6solo()) { 390 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 391 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 392 } else if (is_mx6dl()) { 393 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 394 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 395 } else if (is_mx6dq()) { 396 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 397 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 398 } 399 #elif CONFIG_MX6UL 400 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 401 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 402 #endif 403 404 udelay(100); 405 } 406 407 void board_init_f(ulong dummy) 408 { 409 ccgr_init(); 410 411 /* setup AIPS and disable watchdog */ 412 arch_cpu_init(); 413 414 gpr_init(); 415 416 /* iomux */ 417 SETUP_IOMUX_PADS(uart_pads); 418 419 /* setup GP timer */ 420 timer_init(); 421 422 /* UART clocks enabled and gd valid - init serial console */ 423 preloader_console_init(); 424 425 /* DDR initialization */ 426 spl_dram_init(); 427 } 428