1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <asm/immap.h>
13 #include <asm/io.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
checkboard(void)17 int checkboard(void)
18 {
19 puts("Board: ");
20 puts("Freescale M5235 EVB\n");
21 return 0;
22 };
23
dram_init(void)24 int dram_init(void)
25 {
26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
27 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
28 u32 dramsize, i, dramclk;
29
30 /*
31 * When booting from external Flash, the port-size is less than
32 * the port-size of SDRAM. In this case it is necessary to enable
33 * Data[15:0] on Port Address/Data.
34 */
35 out_8(&gpio->par_ad,
36 GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
37 GPIO_PAR_AD_DATAL);
38
39 /* Initialize PAR to enable SDRAM signals */
40 out_8(&gpio->par_sdram,
41 GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
42 GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
43 GPIO_PAR_SDRAM_SDCS(3));
44
45 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
46 for (i = 0x13; i < 0x20; i++) {
47 if (dramsize == (1 << i))
48 break;
49 }
50 i--;
51
52 if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
53 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
54
55 /* Initialize DRAM Control Register: DCR */
56 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
57 SDRAMC_DCR_RTIM_6CLKS |
58 SDRAMC_DCR_RC((15 * dramclk) >> 4));
59
60 /* Initialize DACR0 */
61 out_be32(&sdram->dacr0,
62 SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
63 SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
64 SDRAMC_DARCn_PS_32);
65 asm("nop");
66
67 /* Initialize DMR0 */
68 out_be32(&sdram->dmr0,
69 ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
70 asm("nop");
71
72 /* Set IP (bit 3) in DACR */
73 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
74
75 /* Wait 30ns to allow banks to precharge */
76 for (i = 0; i < 5; i++) {
77 asm("nop");
78 }
79
80 /* Write to this block to initiate precharge */
81 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
82
83 /* Set RE (bit 15) in DACR */
84 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
85
86 /* Wait for at least 8 auto refresh cycles to occur */
87 for (i = 0; i < 0x2000; i++) {
88 asm("nop");
89 }
90
91 /* Finish the configuration by issuing the MRS. */
92 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
93 asm("nop");
94
95 /* Write to the SDRAM Mode Register */
96 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
97 }
98
99 gd->ram_size = dramsize;
100
101 return 0;
102 };
103
testdram(void)104 int testdram(void)
105 {
106 /* TODO: XXX XXX XXX */
107 printf("DRAM test not implemented!\n");
108
109 return (0);
110 }
111