1 /* 2 * Copyright (C) 2016-2017 Intel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <altera.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <fdtdec.h> 11 #include <miiphy.h> 12 #include <netdev.h> 13 #include <ns16550.h> 14 #include <watchdog.h> 15 #include <asm/arch/misc.h> 16 #include <asm/arch/pinmux.h> 17 #include <asm/arch/reset_manager.h> 18 #include <asm/arch/sdram_arria10.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/io.h> 22 #include <asm/pl310.h> 23 24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 30 31 #if defined(CONFIG_SPL_BUILD) 32 static struct pl310_regs *const pl310 = 33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 34 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = 35 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; 36 #endif 37 38 static struct socfpga_system_manager *sysmgr_regs = 39 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 40 41 /* 42 * DesignWare Ethernet initialization 43 */ 44 #ifdef CONFIG_ETH_DESIGNWARE 45 void dwmac_deassert_reset(const unsigned int of_reset_id, 46 const u32 phymode) 47 { 48 u32 reset; 49 50 if (of_reset_id == EMAC0_RESET) { 51 reset = SOCFPGA_RESET(EMAC0); 52 } else if (of_reset_id == EMAC1_RESET) { 53 reset = SOCFPGA_RESET(EMAC1); 54 } else if (of_reset_id == EMAC2_RESET) { 55 reset = SOCFPGA_RESET(EMAC2); 56 } else { 57 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 58 return; 59 } 60 61 clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], 62 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, 63 phymode); 64 65 /* Release the EMAC controller from reset */ 66 socfpga_per_reset(reset, 0); 67 } 68 #endif 69 70 #if defined(CONFIG_SPL_BUILD) 71 /* 72 + * This function initializes security policies to be consistent across 73 + * all logic units in the Arria 10. 74 + * 75 + * The idea is to set all security policies to be normal, nonsecure 76 + * for all units. 77 + */ 78 static void initialize_security_policies(void) 79 { 80 /* Put OCRAM in non-secure */ 81 writel(0x003f0000, &noc_fw_ocram_base->region0); 82 writel(0x1, &noc_fw_ocram_base->enable); 83 } 84 85 int arch_early_init_r(void) 86 { 87 initialize_security_policies(); 88 89 /* Configure the L2 controller to make SDRAM start at 0 */ 90 writel(0x1, &pl310->pl310_addr_filter_start); 91 92 /* assert reset to all except L4WD0 and L4TIMER0 */ 93 socfpga_per_reset_all(); 94 95 /* configuring the clock based on handoff */ 96 /* TODO: Add call to cm_basic_init() */ 97 98 /* Add device descriptor to FPGA device table */ 99 socfpga_fpga_add(); 100 return 0; 101 } 102 #else 103 int arch_early_init_r(void) 104 { 105 return 0; 106 } 107 #endif 108 109 /* 110 * This function looking the 1st encounter UART peripheral, 111 * and then return its offset of the dedicated/shared IO pin 112 * mux. offset value (zero and above). 113 */ 114 static int find_peripheral_uart(const void *blob, 115 int child, const char *node_name) 116 { 117 int len; 118 fdt_addr_t base_addr = 0; 119 fdt_size_t size; 120 const u32 *cell; 121 u32 value, offset = 0; 122 123 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); 124 if (base_addr != FDT_ADDR_T_NONE) { 125 cell = fdt_getprop(blob, child, "pinctrl-single,pins", 126 &len); 127 if (cell != NULL) { 128 for (; len > 0; len -= (2 * sizeof(u32))) { 129 offset = fdt32_to_cpu(*cell++); 130 value = fdt32_to_cpu(*cell++); 131 /* Found UART peripheral. */ 132 if (value == PINMUX_UART) 133 return offset; 134 } 135 } 136 } 137 return -EINVAL; 138 } 139 140 /* 141 * This function looks up the 1st encounter UART peripheral, 142 * and then return its offset of the dedicated/shared IO pin 143 * mux. UART peripheral is found if the offset is not in negative 144 * value. 145 */ 146 static int is_peripheral_uart_true(const void *blob, 147 int node, const char *child_name) 148 { 149 int child, len; 150 const char *node_name; 151 152 child = fdt_first_subnode(blob, node); 153 154 if (child < 0) 155 return -EINVAL; 156 157 node_name = fdt_get_name(blob, child, &len); 158 159 while (node_name) { 160 if (!strcmp(child_name, node_name)) 161 return find_peripheral_uart(blob, child, node_name); 162 163 child = fdt_next_subnode(blob, child); 164 if (child < 0) 165 break; 166 167 node_name = fdt_get_name(blob, child, &len); 168 } 169 170 return -1; 171 } 172 173 /* 174 * This function looking the 1st encounter UART dedicated IO peripheral, 175 * and then return based address of the 1st encounter UART dedicated 176 * IO peripheral. 177 */ 178 unsigned int dedicated_uart_com_port(const void *blob) 179 { 180 int node; 181 182 node = fdtdec_next_compatible(blob, 0, 183 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); 184 if (node < 0) 185 return 0; 186 187 if (is_peripheral_uart_true(blob, node, "dedicated") >= 0) 188 return SOCFPGA_UART1_ADDRESS; 189 190 return 0; 191 } 192 193 /* 194 * This function looking the 1st encounter UART shared IO peripheral, and then 195 * return based address of the 1st encounter UART shared IO peripheral. 196 */ 197 unsigned int shared_uart_com_port(const void *blob) 198 { 199 int node, ret; 200 201 node = fdtdec_next_compatible(blob, 0, 202 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); 203 if (node < 0) 204 return 0; 205 206 ret = is_peripheral_uart_true(blob, node, "shared"); 207 208 if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 || 209 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 || 210 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3) 211 return SOCFPGA_UART0_ADDRESS; 212 else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 || 213 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 || 214 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3) 215 return SOCFPGA_UART1_ADDRESS; 216 217 return 0; 218 } 219 220 /* 221 * This function looking the 1st encounter UART peripheral, and then return 222 * base address of the 1st encounter UART peripheral. 223 */ 224 unsigned int uart_com_port(const void *blob) 225 { 226 unsigned int ret; 227 228 ret = dedicated_uart_com_port(blob); 229 230 if (ret) 231 return ret; 232 233 return shared_uart_com_port(blob); 234 } 235 236 /* 237 * Print CPU information 238 */ 239 #if defined(CONFIG_DISPLAY_CPUINFO) 240 int print_cpuinfo(void) 241 { 242 const u32 bsel = 243 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 244 245 puts("CPU: Altera SoCFPGA Arria 10\n"); 246 247 printf("BOOT: %s\n", bsel_str[bsel].name); 248 return 0; 249 } 250 #endif 251 252 #ifdef CONFIG_ARCH_MISC_INIT 253 int arch_misc_init(void) 254 { 255 return 0; 256 } 257 #endif 258